[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)
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Thu Feb 15 14:59:42 PST 2024
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git-clang-format --diff 7fc25928233c133a4af1dadf0e060fb5d42ebd4e bc7d09dedd199eb2ae739d625183d9370cac6436 -- clang/test/Driver/amdgpu-features.c llvm/lib/Target/AMDGPU/GCNSubtarget.h llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index c8f02b2482..0e4468a9ea 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -2419,22 +2419,22 @@ bool SIGfx6CacheControl::handleNonAtomicForPreciseMemory(
if (TII->isSMRD(Inst)) { // scalar
if (Inst.mayStore())
return false;
- Wait.DsCnt = 0; // LgkmCnt
- } else { // vector
- if (Inst.mayLoad()) { // vector load
- if (TII->isVMEM(Inst)) // VMEM load
- Wait.LoadCnt = 0; // VmCnt
- else if (TII->isFLAT(Inst)) { // Flat load
- Wait.LoadCnt = 0; // VmCnt
- Wait.DsCnt = 0; // LgkmCnt
- } else // LDS load
- Wait.DsCnt = 0; // LgkmCnt
- } else { // vector store
- if (TII->isVMEM(Inst)) // VMEM store
- Wait.LoadCnt = 0; // VmCnt
- else if (TII->isFLAT(Inst)) { // Flat store
- Wait.LoadCnt = 0; // VmCnt
- Wait.DsCnt = 0; // LgkmCnt
+ Wait.DsCnt = 0; // LgkmCnt
+ } else { // vector
+ if (Inst.mayLoad()) { // vector load
+ if (TII->isVMEM(Inst)) // VMEM load
+ Wait.LoadCnt = 0; // VmCnt
+ else if (TII->isFLAT(Inst)) { // Flat load
+ Wait.LoadCnt = 0; // VmCnt
+ Wait.DsCnt = 0; // LgkmCnt
+ } else // LDS load
+ Wait.DsCnt = 0; // LgkmCnt
+ } else { // vector store
+ if (TII->isVMEM(Inst)) // VMEM store
+ Wait.LoadCnt = 0; // VmCnt
+ else if (TII->isFLAT(Inst)) { // Flat store
+ Wait.LoadCnt = 0; // VmCnt
+ Wait.DsCnt = 0; // LgkmCnt
} else
Wait.DsCnt = 0; // LDS store; LgkmCnt
}
@@ -2476,16 +2476,16 @@ bool SIGfx10CacheControl::handleNonAtomicForPreciseMemory(
if (TII->isSMRD(Inst)) { // scalar
if (Inst.mayStore())
return false;
- Wait.DsCnt = 0; // LgkmCnt
- } else { // vector
- if (Inst.mayLoad()) { // vector load
- if (TII->isVMEM(Inst)) // VMEM load
- Wait.LoadCnt = 0; // VmCnt
- else if (TII->isFLAT(Inst)) { // Flat load
- Wait.LoadCnt = 0; // VmCnt
- Wait.DsCnt = 0; // LgkmCnt
- } else // LDS load
- Wait.DsCnt = 0; // LgkmCnt
+ Wait.DsCnt = 0; // LgkmCnt
+ } else { // vector
+ if (Inst.mayLoad()) { // vector load
+ if (TII->isVMEM(Inst)) // VMEM load
+ Wait.LoadCnt = 0; // VmCnt
+ else if (TII->isFLAT(Inst)) { // Flat load
+ Wait.LoadCnt = 0; // VmCnt
+ Wait.DsCnt = 0; // LgkmCnt
+ } else // LDS load
+ Wait.DsCnt = 0; // LgkmCnt
}
// For some vector instructions, mayLoad() and mayStore() can be both true.
@@ -2567,8 +2567,8 @@ bool SIGfx12CacheControl ::handleNonAtomicForPreciseMemory(
WaitType = AMDGPU::S_WAIT_LOADCNT_DSCNT;
else // LDS load
WaitType = AMDGPU::S_WAIT_DSCNT;
- } else { // vector store
- if (TII->isVMEM(Inst)) // VMEM store
+ } else { // vector store
+ if (TII->isVMEM(Inst)) // VMEM store
WaitType = AMDGPU::S_WAIT_STORECNT;
else if (TII->isFLAT(Inst)) // Flat store
WaitType = AMDGPU::S_WAIT_STORECNT_DSCNT;
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https://github.com/llvm/llvm-project/pull/79236
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