[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Fri Feb 9 10:20:07 PST 2024
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@@ -2136,14 +2136,16 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) {
// bitcast.
if (const auto *FixedSrc = dyn_cast<llvm::FixedVectorType>(SrcTy)) {
if (const auto *ScalableDst = dyn_cast<llvm::ScalableVectorType>(DstTy)) {
- // If we are casting a fixed i8 vector to a scalable 16 x i1 predicate
+ // If we are casting a fixed i8 vector to a scalable i1 predicate
// vector, use a vector insert and bitcast the result.
bool NeedsBitCast = false;
- auto PredType = llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16);
llvm::Type *OrigType = DstTy;
- if (ScalableDst == PredType &&
- FixedSrc->getElementType() == Builder.getInt8Ty()) {
- DstTy = llvm::ScalableVectorType::get(Builder.getInt8Ty(), 2);
+ if (ScalableDst->getElementType()->isIntegerTy(1) &&
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topperc wrote:
I kept the control flow, but removed the `NeedsBitCast` variable. We can compare types to see if the cast is needed.
https://github.com/llvm/llvm-project/pull/76548
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