[llvm] [clang] [RISCV] Add Ssqosid support to -march. (PR #80747)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Mon Feb 5 13:47:25 PST 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/80747
None
>From a92d11432df57ad7172d80157e794ebec63b3410 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 5 Feb 2024 13:46:32 -0800
Subject: [PATCH] [RISCV] Add Ssqosid support to -march.
---
clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++
llvm/docs/RISCVUsage.rst | 3 +++
llvm/docs/ReleaseNotes.rst | 1 +
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
8 files changed, 26 insertions(+)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index add96c0046cc7..e65c8cd43b245 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -163,6 +163,7 @@
// CHECK-NOT: __riscv_smnpm{{.*$}}
// CHECK-NOT: __riscv_ssnpm{{.*$}}
// CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_ssqosid{{.*$}}
// CHECK-NOT: __riscv_supm{{.*$}}
// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
@@ -1612,6 +1613,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_ssqosid1p0 -E -dM %s -menable-experimental-extensions \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
+// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}
+
// Misaligned
// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index c9e99c9b98e37..43c6c3f116c5d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -246,6 +246,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
LLVM implements the `v0.8.1 draft specification <https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf>`
+``experimental-ssqosid``
+ LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.
+
``experimental-zabha``
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`_.
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6ac83961d7cf0..05d8eea3add41 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -102,6 +102,7 @@ Changes to the RISC-V Backend
names in the RISC-V profiles specification are now recognised.
* Codegen support was added for the Zimop (May-Be-Operations) extension.
* The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported.
+* The experimental Ssqosid extension is supported.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 6fe8eb62e2804..d028302b8c4d9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -215,6 +215,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"smnpm", {0, 8}},
{"ssnpm", {0, 8}},
{"sspm", {0, 8}},
+ {"ssqosid", {1, 0}},
{"supm", {0, 8}},
{"zaamo", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 03ccda4561ed8..03e0980402107 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -828,6 +828,10 @@ def FeatureStdExtSstc
: SubtargetFeature<"sstc", "HasStdExtSstc", "true",
"'Sstc' (Supervisor-mode timer interrupts)", []>;
+def FeaturesSsqosid
+ : SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true",
+ "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>;
+
def FeatureStdExtShtvala
: SubtargetFeature<"shtvala", "HasStdExtShtvala", "true",
"'Shtvala' (htval provides all needed values)", []>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 088cc0b90a05a..13635a94d6411 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -121,6 +121,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -249,6 +250,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; CHECK: .attribute 4, 16
@@ -372,6 +374,7 @@
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8"
; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8"
; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8"
+; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV64M: .attribute 5, "rv64i2p1_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -499,6 +502,7 @@
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8"
; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8"
; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
+; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 34b7ee52da320..873037ea0caa2 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -321,6 +321,9 @@
.attribute arch, "rv32i_sscounterenw1p0"
# CHECK: attribute 5, "rv32i2p1_sscounterenw1p0"
+.attribute arch, "rv32i_ssqosid1p0"
+# CHECK: attribute 5, "rv32i2p1_ssqosid1p0"
+
.attribute arch, "rv32i_ssstateen1p0"
# CHECK: attribute 5, "rv32i2p1_ssstateen1p0"
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index ac6066ebdfb94..df4c7f7de8a3d 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -885,6 +885,7 @@ Experimental extensions
smnpm 0.8
ssnpm 0.8
sspm 0.8
+ ssqosid 1.0
supm 0.8
Use -march to specify the target's extension.
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