[clang] [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (PR #76548)

[Craig Topper via cfe-commits]

topperc wrote:

> Generalising this code makes sense, 16 should never have been hardcoded here.
> 
> Is it possible to add a test for the case where the predicate type is not `<vscale x 16 x i1>`?

I rebased, which picked up more tests that are affected for RISC-V. This also pointed out that I missed very similar code in CGCall.cpp so that's been updated now.

https://github.com/llvm/llvm-project/pull/76548