[clang] [llvm] [AArch64][SME] Implement inline-asm clobbers for za/zt0 (PR #79276)
Sander de Smalen via cfe-commits
cfe-commits at lists.llvm.org
Thu Feb 1 00:33:54 PST 2024
================
@@ -507,6 +507,10 @@ bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
return true;
+ // ZA/ZT0 registers are reserved but may be permitted in the clobber list.
+ if (PhysReg.id() == AArch64::ZA || PhysReg.id() == AArch64::ZT0)
----------------
sdesmalen-arm wrote:
```suggestion
if (PhysReg == AArch64::ZA || PhysReg == AArch64::ZT0)
```
https://github.com/llvm/llvm-project/pull/79276
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