[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

[Luke Lau via cfe-commits]

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@@ -764,6 +771,58 @@ def FeatureStdExtSmepmp
     : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
                        "'Smepmp' (Enhanced Physical Memory Protection)", []>;
 
+def FeatureStdExtSsccptr
+    : SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
+                       "'Ssccptr' (Main memory supports page table reads)", []>;
+
+def FeatureStdExtShcounterenvw
+    : SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true",
+                       "'Shcounterenw' (Support writeable enables for any supproted counter)", []>;
+def FeatureStdExtSscounterenvw
+    : SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true",
+                       "'Sscounterenw' (Support writeable enables for any supproted counter)", []>;
+
+def FeatureStdExtSsstateen
+    : SubtargetFeature<"ssstateen", "HasStdExtSsstateen", "true",
+                       "'Ssstateen' (Supervisor-mode view of the state-enable extension)", []>;
+
+def FeatureStdExtSstc
+    : SubtargetFeature<"sstc", "HasStdExtSstc", "true",
+                       "'Sstc' (Supervisor-mode timer interrupts)", []>;
+
+def FeatureStdExtShtvala
+    : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true",
+                       "'Shtvala' (htval provides all needed values)", []>;
+def FeatureStdExtShvstvala
+    : SubtargetFeature<"shvstvala", "HasStdExtShvstvala", "true",
+                       "'Shvstvala' (vstval provides all needed values)", []>;
+def FeatureStdExtSstvala
+    : SubtargetFeature<"sstvala", "HasStdExtSstvala", "true",
+                       "'Sstvala' (stval provides all needed values)", []>;
+
+def FeatureStdExtShvstvecd
+    : SubtargetFeature<"shvstvecd", "HasStdExtShvstvecd", "true",
+                       "'Shvstvecd' (vstvec supports Direct mode)", []>;
+def FeatureStdExtSstvecd
+    : SubtargetFeature<"sstvecd", "HasStdExtSstvecd", "true",
+                       "'Sstvecd' (stvec supports Direct mode)", []>;
+
+def FeatureStdExtSsu64xl
+    : SubtargetFeature<"ssu64xl", "HasStdExtSsu64xl", "true",
+                       "'Ssu64xl' (UXLEN=64 supported)", []>;
+
+def FeaturesStdExtSvade
+    : SubtargetFeature<"svade", "HasStdExtSvade", "true",
+                       "'Svade' (Raise exceptions on improper A/D bits)", []>;
+
+def FeaturesStdExtSvadu
+    : SubtargetFeature<"svadu", "HasStdExtSvadu", "true",
+                       "'Svadu' (Hardware A/D updates)", []>;
+
+def FeaturesStdExtSvbare
+    : SubtargetFeature<"svbare", "HasStdExtSvbare", "true",
+                       "'Svbare' $(satp mode Bare supported)", []>;
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lukel97 wrote:

Should this match the description in https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc#glossary-of-isa-extensions

"Bare mode virtual-memory translation supported"

https://github.com/llvm/llvm-project/pull/79399