[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

[Craig Topper via cfe-commits]

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@@ -692,8 +692,71 @@ define <16 x i64> @fshr_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa sp, 16
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
+; RV32-LABEL: fshr_v16i64:
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topperc wrote:

There's something weird with the CHECK lines here. How do we have CHECK and RV32 and RV64?

https://github.com/llvm/llvm-project/pull/77560