[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

[Craig Topper via cfe-commits]

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@@ -0,0 +1,27 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
+
+#include <riscv_vector.h>
+
+// CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @bar
+vint32m1_t __attribute__((riscv_vector_cc)) bar(vint32m1_t input);
+vint32m1_t test_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
+  vint32m1_t ret;
+  vint32m1_t val;
+  val = __riscv_vle32_v_i32m1(base, vl);
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topperc wrote:

Can we declare the variables on the same line as the assignment?

https://github.com/llvm/llvm-project/pull/77560