[llvm] [clang] [RISCV] Add sifive-p670 processor (PR #79015)
Michael Maitland via cfe-commits
cfe-commits at lists.llvm.org
Mon Jan 22 09:31:15 PST 2024
================
@@ -237,6 +237,43 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
TuneLUIADDIFusion,
TuneAUIPCADDIFusion]>;
+def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicboz,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZiccif,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZihpm,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZfhmin,
+ FeatureStdExtV,
+ FeatureStdExtZvl128b,
+ FeatureStdExtZvbb,
+ FeatureStdExtZvknc,
+ FeatureStdExtZvkng,
+ FeatureStdExtZvksc,
+ FeatureStdExtZvksg,
+ FeatureFastUnalignedAccess],
+ [TuneNoDefaultUnroll,
+ TuneConditionalCompressedMoveFusion,
+ TuneLUIADDIFusion,
----------------
michaelmaitland wrote:
Updated.
https://github.com/llvm/llvm-project/pull/79015
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