[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Mon Jan 22 09:28:52 PST 2024
================
@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands(
if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions())
return false;
+ // Don't sink splat operands if the target prefers it. Some targets requires
----------------
topperc wrote:
This change is not mentioned in the patch description
https://github.com/llvm/llvm-project/pull/79015
More information about the cfe-commits
mailing list