[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

[James Y Knight via cfe-commits]

jyknight wrote:

Yes, that's an acceptable/correct solution in that circumstance. Given we already have a forced-atomics option, IMO it probably makes sense to still require users to specify that explicitly, rather than effectively defaulting it to on with Zaamo.

However, I must say, I cannot understand why this is even a thing that anyone would want. Why would anyone design a single-processor RISCV system that doesn't implement LR/SC? If you don't have the issue of coherent memory across multiple CPUs, LR/SC is utterly trivial to implement -- it's 1 bit of hidden state, indicating whether there is an active reservation. You set the bit in LR. In SC, you check if it's set; if so, execute the store, clear the bit, and return success, otherwise return failure. So, like...why...

https://github.com/llvm/llvm-project/pull/77424