[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Tue Jan 16 20:40:01 PST 2024
================
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector<std::string> NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension target features.
+ const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ if (I != FeaturesVec.end()) {
+ std::vector<std::string> OverrideFeatures(std::next(I), FeaturesVec.end());
+
+ // Add back any non ISA extension features, e.g. +relax.
+ auto IsNonISAExtFeature = [](StringRef Feature) {
+ assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+ StringRef Ext = Feature.substr(1); // drop the +/-
+ return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+ };
+ llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+ std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
- auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+ return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+ }
+
+ // Otherwise, parse the features and add any implied extensions.
+ std::vector AllFeatures = FeaturesVec;
----------------
topperc wrote:
This might need to be `std::vector<std::string>` Also I'm not we should copy the vector here just to rename it?
https://github.com/llvm/llvm-project/pull/77426
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