[clang] [llvm] riscv vector cc (PR #77560)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Thu Jan 11 12:49:44 PST 2024
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@@ -1416,14 +1560,46 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
// first in the epilogue. It increases the opportunity to avoid the
// load-to-use data hazard between loading RA and return by RA.
// loadRegFromStackSlot can insert multiple instructions.
+ //
+ //
+ // We first change the restore order for scalar and vector
+ // callee-saved registers as the layout shown below:
+ //
+ // Epilog restore order (original):
+ // ----------------------------
+ // RVV objects
----------------
topperc wrote:
The epilog doesn't "restore" RVV objects. Other than adjusting the stack pointer. I'm not sure what this is illustrating
https://github.com/llvm/llvm-project/pull/77560
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