[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
Luke Lau via cfe-commits
cfe-commits at lists.llvm.org
Thu Jan 11 00:04:59 PST 2024
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++++++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++++++++++++++++++++++++++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++++++++++++++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..c5c8f86a72d9d7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
+ {"za128rs", RISCVExtensionVersion{1, 0}},
+ {"za64rs", RISCVExtensionVersion{1, 0}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"zba", RISCVExtensionVersion{1, 0}},
@@ -121,9 +123,14 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zhinx", RISCVExtensionVersion{1, 0}},
{"zhinxmin", RISCVExtensionVersion{1, 0}},
+ {"zic64b", RISCVExtensionVersion{1, 0}},
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
+ {"ziccamoa", RISCVExtensionVersion{1, 0}},
+ {"ziccif", RISCVExtensionVersion{1, 0}},
+ {"zicclsm", RISCVExtensionVersion{1, 0}},
+ {"ziccrse", RISCVExtensionVersion{1, 0}},
{"zicntr", RISCVExtensionVersion{2, 0}},
{"zicsr", RISCVExtensionVersion{2, 0}},
{"zifencei", RISCVExtensionVersion{2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..17ed2a3aa2c57c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+ : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+ : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+ : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+ : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision Floating-Point)">;
+def FeatureStdExtZic64b
+ : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
+ "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true",
+ "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..8373ead932a695 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -130,6 +130,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZK %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zic64b %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIC64B %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOM %s
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOP %s
@@ -149,6 +150,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV64XTHEADMEMPAIR %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
+; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s
; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
; RUN: llc -mtriple=riscv64 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
@@ -156,6 +159,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
; RUN: llc -mtriple=riscv64 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMP %s
; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s
+; RUN: llc -mtriple=riscv64 -mattr=+ziccamoa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOA %s
+; RUN: llc -mtriple=riscv64 -mattr=+ziccif %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCIF %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicclsm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCLSM %s
+; RUN: llc -mtriple=riscv64 -mattr=+ziccrse %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCRSE %s
; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
@@ -319,8 +326,11 @@
; RV64COMBINEINTOZK: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+; RV64ZIC64B: .attribute 5, "rv64i2p1_zic64b1p0"
; RV64ZICBOM: .attribute 5, "rv64i2p1_zicbom1p0"
; RV64ZICBOZ: .attribute 5, "rv64i2p1_zicboz1p0"
+; RV64ZA64RS: .attribute 5, "rv64i2p1_za64rs1p0"
+; RV64ZA128RS: .attribute 5, "rv64i2p1_za128rs1p0"
; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0"
; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0"
@@ -345,6 +355,10 @@
; RV64ZCD: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
+; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0"
+; RV64ZICCIF: .attribute 5, "rv64i2p1_ziccif1p0"
+; RV64ZICCLSM: .attribute 5, "rv64i2p1_zicclsm1p0"
+; RV64ZICCRSE: .attribute 5, "rv64i2p1_ziccrse1p0"
; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr2p0_zicsr2p0"
>From 80ea83cf289f84c4978680661b784a8e8e5d12af Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 10 Jan 2024 01:54:35 +0700
Subject: [PATCH 2/7] Update RISCVISAInfoTest.cpp
---
llvm/unittests/Support/RISCVISAInfoTest.cpp | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 42759f30fd1bc3..45452c6cff8fc7 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -665,9 +665,14 @@ R"(All available -march extensions for RISC-V
c 2.0
v 1.0
h 1.0
+ zic64b 1.0
zicbom 1.0
zicbop 1.0
zicboz 1.0
+ ziccamoa 1.0
+ ziccif 1.0
+ zicclsm 1.0
+ ziccrse 1.0
zicntr 2.0
zicsr 2.0
zifencei 2.0
@@ -675,6 +680,8 @@ R"(All available -march extensions for RISC-V
zihintpause 2.0
zihpm 2.0
zmmul 1.0
+ za128rs 1.0
+ za64rs 1.0
zawrs 1.0
zfa 1.0
zfh 1.0
>From 21c4cadeacb5c82b9fd6b1e9a314daec67c056ed Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 10 Jan 2024 13:50:49 +0700
Subject: [PATCH 3/7] Fix typo
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 17ed2a3aa2c57c..51f77a56062e4a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -574,8 +574,8 @@ def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
-def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
- "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
+def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
+ "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true",
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
>From 3d7bd37f7704b18d350a579266178729a8e44cea Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 10 Jan 2024 14:12:31 +0700
Subject: [PATCH 4/7] Update riscv-target-features.c and attribute-arch.s
---
.../test/Preprocessor/riscv-target-features.c | 63 +++++++++++++++++++
llvm/test/MC/RISCV/attribute-arch.s | 23 ++++++-
2 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 02d8d34116f804..262e23caf90123 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -50,6 +50,8 @@
// CHECK-NOT: __riscv_xtheadsync {{.*$}}
// CHECK-NOT: __riscv_xtheadvdot {{.*$}}
// CHECK-NOT: __riscv_xventanacondops {{.*$}}
+// CHECK-NOT: __riscv_za128rs {{.*$}}
+// CHECK-NOT: __riscv_za64rs {{.*$}}
// CHECK-NOT: __riscv_zawrs {{.*$}}
// CHECK-NOT: __riscv_zba {{.*$}}
// CHECK-NOT: __riscv_zbb {{.*$}}
@@ -71,9 +73,14 @@
// CHECK-NOT: __riscv_zfinx {{.*$}}
// CHECK-NOT: __riscv_zhinx {{.*$}}
// CHECK-NOT: __riscv_zhinxmin {{.*$}}
+// CHECK-NOT: __riscv_zic64b {{.*$}}
// CHECK-NOT: __riscv_zicbom {{.*$}}
// CHECK-NOT: __riscv_zicbop {{.*$}}
// CHECK-NOT: __riscv_zicboz {{.*$}}
+// CHECK-NOT: __riscv_ziccamoa {{.*$}}
+// CHECK-NOT: __riscv_ziccif {{.*$}}
+// CHECK-NOT: __riscv_zicclsm {{.*$}}
+// CHECK-NOT: __riscv_ziccrse {{.*$}}
// CHECK-NOT: __riscv_zicntr {{.*$}}
// CHECK-NOT: __riscv_zicsr {{.*$}}
// CHECK-NOT: __riscv_zifencei {{.*$}}
@@ -451,6 +458,22 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32iza128rs -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZA128RS-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64iza128rs -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZA128RS-EXT %s
+// CHECK-ZA128RS-EXT: __riscv_za128rs 1000000{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32iza64rs -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZA64RS-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64iza64rs -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZA64RS-EXT %s
+// CHECK-ZA64RS-EXT: __riscv_za64rs 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izawrs -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAWRS-EXT %s
@@ -645,6 +668,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZHINXMIN-EXT %s
// CHECK-ZHINXMIN-EXT: __riscv_zhinxmin 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32izic64b -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIC64B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izic64b -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIC64B-EXT %s
+// CHECK-ZIC64B-EXT: __riscv_zic64b 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izicbom -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOM-EXT %s
@@ -669,6 +700,38 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICBOZ-EXT %s
// CHECK-ZICBOZ-EXT: __riscv_zicboz 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32iziccamoa -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOA-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64iziccamoa -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOA-EXT %s
+// CHECK-ZICCAMOA-EXT: __riscv_ziccamoa 1000000{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32iziccif -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCIF-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64iziccif -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCIF-EXT %s
+// CHECK-ZICCIF-EXT: __riscv_ziccif 1000000{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32izicclsm -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCLSM-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izicclsm -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCLSM-EXT %s
+// CHECK-ZICCLSM-EXT: __riscv_zicclsm 1000000{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32iziccrse -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCRSE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64iziccrse -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCRSE-EXT %s
+// CHECK-ZICCRSE-EXT: __riscv_ziccrse 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izicntr -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICNTR-EXT %s
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 4f8a8dfdbcec90..693c9fd150c3a9 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -91,6 +91,9 @@
.attribute arch, "rv32ifdzve64d"
# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32izic64b"
+# CHECK: attribute 5, "rv32i2p1_zic64b1p0"
+
.attribute arch, "rv32izicbom"
# CHECK: attribute 5, "rv32i2p1_zicbom1p0"
@@ -100,6 +103,18 @@
.attribute arch, "rv32izicbop"
# CHECK: attribute 5, "rv32i2p1_zicbop1p0"
+.attribute arch, "rv32iziccamoa"
+# CHECK: attribute 5, "rv32i2p1_ziccamoa1p0"
+
+.attribute arch, "rv32iziccif"
+# CHECK: attribute 5, "rv32i2p1_ziccif1p0"
+
+.attribute arch, "rv32izicclsm"
+# CHECK: attribute 5, "rv32i2p1_zicclsm1p0"
+
+.attribute arch, "rv32iziccrse"
+# CHECK: attribute 5, "rv32i2p1_ziccrse1p0"
+
## Experimental extensions require version string to be explicitly specified
.attribute arch, "rv32izba1p0"
@@ -125,7 +140,7 @@
.attribute arch, "rv32i_zve64x_zvkn1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
-
+
.attribute arch, "rv32i_zve64x_zvknc1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
@@ -249,6 +264,12 @@
.attribute arch, "rv64i_xsfvcp"
# CHECK: attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"
+.attribute arch, "rv32iza128rs1p0"
+# CHECK: attribute 5, "rv32i2p1_za128rs1p0"
+
+.attribute arch, "rv32iza64rs1p0"
+# CHECK: attribute 5, "rv32i2p1_za64rs1p0"
+
.attribute arch, "rv32izawrs1p0"
# CHECK: attribute 5, "rv32i2p1_zawrs1p0"
>From 267e584eb2dd3cd1a298c6ee56c6c2f112e67fa3 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 10 Jan 2024 14:20:25 +0700
Subject: [PATCH 5/7] Update RISCVUsage.txt
---
llvm/docs/RISCVUsage.rst | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 99c7146825f5ee..5c8f45766873e5 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -96,6 +96,8 @@ on support follow.
``Svnapot`` Assembly Support
``Svpbmt`` Supported
``V`` Supported
+ ``Za128rs`` Supported
+ ``Za64rs`` Supported
``Zawrs`` Assembly Support
``Zba`` Supported
``Zbb`` Supported
@@ -117,9 +119,14 @@ on support follow.
``Zfinx`` Supported
``Zhinx`` Supported
``Zhinxmin`` Supported
+ ``Zic64b`` Supported
``Zicbom`` Assembly Support
``Zicbop`` Supported
``Zicboz`` Assembly Support
+ ``Ziccamoa`` Supported
+ ``Ziccif`` Supported
+ ``Zicclsm`` Supported
+ ``Ziccrse`` Supported
``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
``Zicsr`` (`See Note <#riscv-i2p1-note>`__)
``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
>From 171c6beb0654eaed8e4ed9c92efa38b5ce97ce02 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 10 Jan 2024 21:32:08 +0700
Subject: [PATCH 6/7] Update release notes
---
llvm/docs/ReleaseNotes.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 52610e7de18751..0621bf9b2423ab 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -151,6 +151,9 @@ Changes to the RISC-V Backend
"SiFive Custom Instruction Extension" as SiFive defines it. The LLVM project
needs to work with SiFive to define and document real extension names for
individual CSRs and instructions.
+* Support was added for the Ziccif, Ziccrse, Ziccamoa, Zicclsm, Za64rs, Za128rs
+ and Zic64b extensions which were introduced as a part of the RISC-V Profiles
+ specification.
Changes to the WebAssembly Backend
----------------------------------
>From b54279fd8fbdc9f8541396536fc56864248a6a81 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Thu, 11 Jan 2024 15:04:05 +0700
Subject: [PATCH 7/7] Add note about the profiles specification in
RISCVUsage.rst
---
llvm/docs/RISCVUsage.rst | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5c8f45766873e5..f2f7ee1ca90b78 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -96,8 +96,8 @@ on support follow.
``Svnapot`` Assembly Support
``Svpbmt`` Supported
``V`` Supported
- ``Za128rs`` Supported
- ``Za64rs`` Supported
+ ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
+ ``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Zawrs`` Assembly Support
``Zba`` Supported
``Zbb`` Supported
@@ -119,14 +119,14 @@ on support follow.
``Zfinx`` Supported
``Zhinx`` Supported
``Zhinxmin`` Supported
- ``Zic64b`` Supported
+ ``Zic64b`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Zicbom`` Assembly Support
``Zicbop`` Supported
``Zicboz`` Assembly Support
- ``Ziccamoa`` Supported
- ``Ziccif`` Supported
- ``Zicclsm`` Supported
- ``Ziccrse`` Supported
+ ``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__)
+ ``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__)
+ ``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)
+ ``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
``Zicsr`` (`See Note <#riscv-i2p1-note>`__)
``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
@@ -206,6 +206,11 @@ Supported
``zicntr``, ``zicsr``, ``zifencei``, ``zihpm``
Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions, but were no longer required by the base ISA. This change is partially described in "Preface to Document Version 20190608-Base-Ratified" from the specification document (the ``zicntr`` and ``zihpm`` bits are not mentioned). LLVM currently implements version 2.1 of the base specification. To maintain compatibility, instructions from these extensions are accepted without being in the ``-march`` string. LLVM also allows the explicit specification of the extensions in an ``-march`` string.
+.. _riscv-profiles-extensions-note:
+
+``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``
+ These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`_. They do not introduce any new features themselves, but instead describe existing hardware features.
+
Experimental Extensions
=======================
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