[llvm] [clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)
Kai Luo via cfe-commits
cfe-commits at lists.llvm.org
Wed Jan 10 19:20:35 PST 2024
https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/77557
>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Wed, 10 Jan 2024 05:29:22 +0000
Subject: [PATCH 1/4] Alias
---
clang/lib/Basic/Targets/PPC.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..fa86d93b141180 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -803,7 +803,7 @@ const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
{{"fr22"}, "f22"}, {{"fr23"}, "f23"}, {{"fr24"}, "f24"},
{{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"},
{{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"},
- {{"fr31"}, "f31"}, {{"cc"}, "cr0"},
+ {{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"}, "xer"},
};
ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
>From aaee97fb9f7bef5ff4e3f845fa29d45e9c7a83b0 Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Wed, 10 Jan 2024 05:56:27 +0000
Subject: [PATCH 2/4] CA aliasing to XER
---
clang/lib/Basic/Targets/PPC.cpp | 3 +++
clang/test/CodeGen/ppc-register-names.c | 14 ++++++++++++++
2 files changed, 17 insertions(+)
create mode 100644 clang/test/CodeGen/ppc-register-names.c
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa86d93b141180..abf685f8883971 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,6 +782,9 @@ ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const {
const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
// While some of these aliases do map to different registers
// they still share the same register name.
+ // Strictly speaking, "ca" is a subregister of "xer". However
+ // currently we don't model other bit fields of "xer", so treat
+ // "ca" aliasing to "xer".
{{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
{{"3"}, "r3"}, {{"4"}, "r4"}, {{"5"}, "r5"},
{{"6"}, "r6"}, {{"7"}, "r7"}, {{"8"}, "r8"},
diff --git a/clang/test/CodeGen/ppc-register-names.c b/clang/test/CodeGen/ppc-register-names.c
new file mode 100644
index 00000000000000..209488c2e5f1ae
--- /dev/null
+++ b/clang/test/CodeGen/ppc-register-names.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o - | \
+// RUN: FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - | \
+// RUN: FileCheck %s
+
+void test_function(void) {
+ asm volatile("":::"ca");
+ asm volatile("":::"xer");
+ // CHECK: call void asm sideeffect "", "~{xer}"()
+ // CHECK: call void asm sideeffect "", "~{xer}"()
+ // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+ // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+}
>From f871c97964ca600ad62f04993b93912203a8cd02 Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Wed, 10 Jan 2024 06:08:04 +0000
Subject: [PATCH 3/4] Adjust comment
---
clang/lib/Basic/Targets/PPC.cpp | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index abf685f8883971..01f58b57f6096f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,9 +782,8 @@ ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const {
const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
// While some of these aliases do map to different registers
// they still share the same register name.
- // Strictly speaking, "ca" is a subregister of "xer". However
- // currently we don't model other bit fields of "xer", so treat
- // "ca" aliasing to "xer".
+ // Strictly speaking, "ca" is a subregister of "xer". However currently we
+ // don't model other bit fields of "xer", so treat "ca" aliased to "xer".
{{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
{{"3"}, "r3"}, {{"4"}, "r4"}, {{"5"}, "r5"},
{{"6"}, "r6"}, {{"7"}, "r7"}, {{"8"}, "r8"},
@@ -806,7 +805,7 @@ const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
{{"fr22"}, "f22"}, {{"fr23"}, "f23"}, {{"fr24"}, "f24"},
{{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"},
{{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"},
- {{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"}, "xer"},
+ {{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"}, "xer"},
};
ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
>From 9057159a874ce4693aeee12d36c86ed0ee409c2e Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Thu, 11 Jan 2024 03:20:24 +0000
Subject: [PATCH 4/4] Backend stuff
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 8 ++++---
.../PowerPC/inline-asm-clobber-xer-ca.ll | 21 +++++++++++++++++++
2 files changed, 26 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-clobber-xer-ca.ll
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 8a37e40414eeea..9f80f6cf85eb35 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
-// Carry bit. In the architecture this is really bit 0 of the XER register
-// (which really is SPR register 1); this is the only bit interesting to a
-// compiler.
+// Carry bit. In the architecture this is really bit 2 of the 32-bit XER
+// register (which really is SPR register 1); this is the only bit interesting
+// to a compiler.
def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {
let Aliases = [XER];
}
@@ -473,8 +473,10 @@ def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {
}
def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
+
def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
let CopyCost = -1;
+ let isAllocatable = 0;
}
// Make AllocationOrder as similar as G8RC's to avoid potential spilling.
diff --git a/llvm/test/CodeGen/PowerPC/inline-asm-clobber-xer-ca.ll b/llvm/test/CodeGen/PowerPC/inline-asm-clobber-xer-ca.ll
new file mode 100644
index 00000000000000..747c98309cef25
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/inline-asm-clobber-xer-ca.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -stop-after=finalize-isel < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-- -stop-after=finalize-isel < %s | FileCheck --check-prefix=CHECK-32 %s
+; FIXME: `implicit-def early-clobber $carry` should be generated for `call void asm sideeffect "", "~{ca}"()`.
+define void @f() {
+ ; CHECK-LABEL: name: f
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $xer
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
+ ;
+ ; CHECK-32-LABEL: name: f
+ ; CHECK-32: bb.0.entry:
+ ; CHECK-32-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $xer
+ ; CHECK-32-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */
+ ; CHECK-32-NEXT: BLR implicit $lr, implicit $rm
+entry:
+ call void asm sideeffect "", "~{xer}"()
+ call void asm sideeffect "", "~{ca}"()
+ ret void
+}
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