[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

[Nemanja Ivanovic via cfe-commits]

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@@ -38,3 +40,14 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
 // Same as CSR_Interrupt, but including all 64-bit FP registers.
 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
                                              (sequence "F%u_D", 0, 31))>;
+
+// Same as CSR_Interrupt, but excluding X16-X31.
+def CSR_Interrupt_RVE : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 15))>;
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nemanjai wrote:

Minor nit: I think it would be nice if the code reads as clearly as this comment does.
Namely `(sub CSR_Interrupt, (sequence "X%u, 16, 31))`
Similarly below.

https://github.com/llvm/llvm-project/pull/76777