[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

[Craig Topper via cfe-commits]

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@@ -109,6 +115,11 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // beginning with 'x0' for instructions that take register pairs.
   markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);
 
+  // There are only 16 GPRs for RVE.
+  if (STI.isRVE())
+    for (size_t Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
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topperc wrote:

`MCPhysReg`.  Registers aren't size_t.

https://github.com/llvm/llvm-project/pull/76777