[clang-tools-extra] [mlir] [llvm] [clang] [clangd] Fix is spelled in source bug (PR #76668)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Jan 1 07:45:25 PST 2024
https://github.com/schenka0 updated https://github.com/llvm/llvm-project/pull/76668
>From fd5e586d807fa4532f26188822ac5790202673bc Mon Sep 17 00:00:00 2001
From: schenka0 <154034018+schenka0 at users.noreply.github.com>
Date: Mon, 1 Jan 2024 01:31:05 -0500
Subject: [PATCH 1/7] Check for invalid SLocEntry before getting spelling
---
clang-tools-extra/clangd/SourceCode.cpp | 7 ++++++-
.../clangd/unittests/SourceCodeTests.cpp | 15 +++++++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/clang-tools-extra/clangd/SourceCode.cpp b/clang-tools-extra/clangd/SourceCode.cpp
index 835038423fdf37..8c573cc6fc064a 100644
--- a/clang-tools-extra/clangd/SourceCode.cpp
+++ b/clang-tools-extra/clangd/SourceCode.cpp
@@ -232,7 +232,12 @@ bool isSpelledInSource(SourceLocation Loc, const SourceManager &SM) {
if (Loc.isFileID())
return true;
auto Spelling = SM.getDecomposedSpellingLoc(Loc);
- StringRef SpellingFile = SM.getSLocEntry(Spelling.first).getFile().getName();
+ bool InvalidSLocEntry = false;
+ const auto SLocEntry = SM.getSLocEntry(Spelling.first, &InvalidSLocEntry);
+ if (InvalidSLocEntry) {
+ return false;
+ }
+ const StringRef SpellingFile = SLocEntry.getFile().getName();
if (SpellingFile == "<scratch space>")
return false;
if (SpellingFile == "<built-in>")
diff --git a/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp b/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp
index 08abde87df6d4d..5dced4d317c605 100644
--- a/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp
+++ b/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp
@@ -813,6 +813,21 @@ TEST(SourceCodeTests, isKeywords) {
EXPECT_FALSE(isKeyword("override", LangOpts));
}
+TEST(SourceCodeTests, isSpelledInSource) {
+ Annotations Test(R"cpp(
+ int abc = 1;
+ )cpp");
+
+ ParsedAST AST = TestTU::withCode(Test.code()).build();
+ llvm::errs() << Test.code();
+ const SourceManager &SM = AST.getSourceManager();
+
+ EXPECT_TRUE(
+ isSpelledInSource(SM.getLocForStartOfFile(SM.getMainFileID()), SM));
+ EXPECT_TRUE(isSpelledInSource(SourceLocation(), SM));
+ EXPECT_FALSE(isSpelledInSource(SourceLocation::getFromRawEncoding(-1), SM));
+}
+
struct IncrementalTestStep {
llvm::StringRef Src;
llvm::StringRef Contents;
>From 6611e5a1259b79faacfe37acc10e2d65c7dbf52d Mon Sep 17 00:00:00 2001
From: Brad Smith <brad at comstyle.com>
Date: Mon, 1 Jan 2024 04:31:27 -0500
Subject: [PATCH 2/7] [Driver][Solaris] Remove reachable llvm_unreachable
(#76645)
Remove the llvm_unreachable from getSolarisLibSuffix(). The code path is
reachable. In the case of an unsupported architecture we're not worrying
about trying to actually find the library paths, and I don't think it
makes sense for the Driver to crash.
Fixes #58334
---
clang/lib/Driver/ToolChains/Solaris.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Solaris.cpp b/clang/lib/Driver/ToolChains/Solaris.cpp
index 9a9792d019d5ed..200ac46aa53409 100644
--- a/clang/lib/Driver/ToolChains/Solaris.cpp
+++ b/clang/lib/Driver/ToolChains/Solaris.cpp
@@ -295,13 +295,12 @@ static StringRef getSolarisLibSuffix(const llvm::Triple &Triple) {
switch (Triple.getArch()) {
case llvm::Triple::x86:
case llvm::Triple::sparc:
+ default:
break;
case llvm::Triple::x86_64:
return "/amd64";
case llvm::Triple::sparcv9:
return "/sparcv9";
- default:
- llvm_unreachable("Unsupported architecture");
}
return "";
}
>From 96d6738fd437a5d2e18780dfe8a467f9626cf7f9 Mon Sep 17 00:00:00 2001
From: yonillasky <yonillasky at users.noreply.github.com>
Date: Mon, 1 Jan 2024 12:39:29 +0200
Subject: [PATCH 3/7] [MLIR][LLVM] Add llvm.intr.coro.promise (#76640)
Added to allow generating these intrinsics in out-of-tree MLIR passes.
Co-authored-by: Yoni Lavi <yoni.lavi at nextsilicon.com>
---
mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td | 8 ++++++++
mlir/test/Target/LLVMIR/Import/intrinsic.ll | 8 ++++++++
mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir | 8 ++++++++
3 files changed, 24 insertions(+)
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
index a798cad6037776..a4f08fb92da903 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
@@ -435,6 +435,14 @@ def LLVM_CoroResumeOp : LLVM_IntrOp<"coro.resume", [], [], [], 0> {
let assemblyFormat = "$handle attr-dict `:` qualified(type($handle))";
}
+def LLVM_CoroPromiseOp : LLVM_IntrOp<"coro.promise", [], [], [], 1> {
+ let arguments = (ins LLVM_AnyPointer:$handle,
+ I32:$align,
+ I1:$from);
+ let results = (outs LLVM_AnyPointer:$res);
+ let assemblyFormat = "$handle `,` $align `,` $from attr-dict `:` functional-type(operands, results)";
+}
+
//
// Debug function intrinsics.
//
diff --git a/mlir/test/Target/LLVMIR/Import/intrinsic.ll b/mlir/test/Target/LLVMIR/Import/intrinsic.ll
index f52ad6b56d141d..1ec9005458c50b 100644
--- a/mlir/test/Target/LLVMIR/Import/intrinsic.ll
+++ b/mlir/test/Target/LLVMIR/Import/intrinsic.ll
@@ -720,6 +720,13 @@ define void @coro_resume(ptr %0) {
ret void
}
+; CHECK-LABEL: llvm.func @coro_promise
+define void @coro_promise(ptr %0, i32 %1, i1 %2) {
+ ; CHECK: llvm.intr.coro.promise %{{.*}}, %{{.*}}, %{{.*}} : (!llvm.ptr, i32, i1) -> !llvm.ptr
+ %4 = call ptr @llvm.coro.promise(ptr %0, i32 %1, i1 %2)
+ ret void
+}
+
; CHECK-LABEL: llvm.func @eh_typeid_for
define void @eh_typeid_for(ptr %0) {
; CHECK: llvm.intr.eh.typeid.for %{{.*}} : (!llvm.ptr) -> i32
@@ -1046,6 +1053,7 @@ declare i8 @llvm.coro.suspend(token, i1)
declare i1 @llvm.coro.end(ptr, i1, token)
declare ptr @llvm.coro.free(token, ptr nocapture readonly)
declare void @llvm.coro.resume(ptr)
+declare ptr @llvm.coro.promise(ptr nocapture, i32, i1)
declare i32 @llvm.eh.typeid.for(ptr)
declare ptr @llvm.stacksave.p0()
declare ptr addrspace(1) @llvm.stacksave.p1()
diff --git a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
index 1c0aa8d3407ac6..fc2e0fd201a738 100644
--- a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
@@ -712,6 +712,13 @@ llvm.func @coro_resume(%arg0: !llvm.ptr) {
llvm.return
}
+// CHECK-LABEL: @coro_promise
+llvm.func @coro_promise(%arg0: !llvm.ptr, %arg1 : i32, %arg2 : i1) {
+ // CHECK: call ptr @llvm.coro.promise
+ %0 = llvm.intr.coro.promise %arg0, %arg1, %arg2 : (!llvm.ptr, i32, i1) -> !llvm.ptr
+ llvm.return
+}
+
// CHECK-LABEL: @eh_typeid_for
llvm.func @eh_typeid_for(%arg0 : !llvm.ptr) {
// CHECK: call i32 @llvm.eh.typeid.for
@@ -1056,6 +1063,7 @@ llvm.func @ssa_copy(%arg: f32) -> f32 {
// CHECK-DAG: declare i1 @llvm.coro.end(ptr, i1, token)
// CHECK-DAG: declare ptr @llvm.coro.free(token, ptr nocapture readonly)
// CHECK-DAG: declare void @llvm.coro.resume(ptr)
+// CHECK-DAG: declare ptr @llvm.coro.promise(ptr nocapture, i32, i1)
// CHECK-DAG: declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
// CHECK-DAG: declare <8 x i32> @llvm.vp.mul.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
>From bbf37dfaa4189ee18a8032cea091d8dc6436330b Mon Sep 17 00:00:00 2001
From: DianQK <dianqk at dianqk.net>
Date: Mon, 1 Jan 2024 20:41:40 +0800
Subject: [PATCH 4/7] [SimplifyCFG] Regenerate test checks (NFC)
Use `UTC_ARGS: --version 4`.
---
.../SimplifyCFG/switch-dead-default.ll | 55 +++++++++++--------
1 file changed, 31 insertions(+), 24 deletions(-)
diff --git a/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll b/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
index 1662bb99f27bcc..7c0d5e4f2b653c 100644
--- a/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
+++ b/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
@@ -1,12 +1,13 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt %s -S -passes='simplifycfg<switch-to-lookup>' -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
declare void @foo(i32)
define void @test(i1 %a) {
-; CHECK-LABEL: @test(
-; CHECK-NEXT: [[A_OFF:%.*]] = add i1 [[A:%.*]], true
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: i1 [[A:%.*]]) {
+; CHECK-NEXT: [[A_OFF:%.*]] = add i1 [[A]], true
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i1 [[A_OFF]], true
; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: common.ret:
@@ -32,12 +33,13 @@ default:
}
define void @test2(i2 %a) {
-; CHECK-LABEL: @test2(
-; CHECK-NEXT: switch i2 [[A:%.*]], label [[DOTUNREACHABLEDEFAULT:%.*]] [
-; CHECK-NEXT: i2 0, label [[CASE0:%.*]]
-; CHECK-NEXT: i2 1, label [[CASE1:%.*]]
-; CHECK-NEXT: i2 -2, label [[CASE2:%.*]]
-; CHECK-NEXT: i2 -1, label [[CASE3:%.*]]
+; CHECK-LABEL: define void @test2(
+; CHECK-SAME: i2 [[A:%.*]]) {
+; CHECK-NEXT: switch i2 [[A]], label [[DOTUNREACHABLEDEFAULT:%.*]] [
+; CHECK-NEXT: i2 0, label [[CASE0:%.*]]
+; CHECK-NEXT: i2 1, label [[CASE1:%.*]]
+; CHECK-NEXT: i2 -2, label [[CASE2:%.*]]
+; CHECK-NEXT: i2 -1, label [[CASE3:%.*]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
@@ -80,11 +82,12 @@ default:
; This one is a negative test - we know the value of the default,
; but that's about it
define void @test3(i2 %a) {
-; CHECK-LABEL: @test3(
-; CHECK-NEXT: switch i2 [[A:%.*]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT: i2 0, label [[CASE0:%.*]]
-; CHECK-NEXT: i2 1, label [[CASE1:%.*]]
-; CHECK-NEXT: i2 -2, label [[CASE2:%.*]]
+; CHECK-LABEL: define void @test3(
+; CHECK-SAME: i2 [[A:%.*]]) {
+; CHECK-NEXT: switch i2 [[A]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT: i2 0, label [[CASE0:%.*]]
+; CHECK-NEXT: i2 1, label [[CASE1:%.*]]
+; CHECK-NEXT: i2 -2, label [[CASE2:%.*]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
@@ -122,10 +125,11 @@ default:
; Negative test - check for possible overflow when computing
; number of possible cases.
define void @test4(i128 %a) {
-; CHECK-LABEL: @test4(
-; CHECK-NEXT: switch i128 [[A:%.*]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT: i128 0, label [[CASE0:%.*]]
-; CHECK-NEXT: i128 1, label [[CASE1:%.*]]
+; CHECK-LABEL: define void @test4(
+; CHECK-SAME: i128 [[A:%.*]]) {
+; CHECK-NEXT: switch i128 [[A]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT: i128 0, label [[CASE0:%.*]]
+; CHECK-NEXT: i128 1, label [[CASE1:%.*]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
@@ -155,8 +159,9 @@ default:
; All but one bit known zero
define void @test5(i8 %a) {
-; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[A:%.*]], 2
+; CHECK-LABEL: define void @test5(
+; CHECK-SAME: i8 [[A:%.*]]) {
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[A]], 2
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], -1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1
@@ -187,8 +192,9 @@ default:
;; All but one bit known one
define void @test6(i8 %a) {
-; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[A:%.*]], -2
+; CHECK-LABEL: define void @test6(
+; CHECK-SAME: i8 [[A:%.*]]) {
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[A]], -2
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], -2
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], 1
@@ -222,8 +228,9 @@ default:
; Check that we can eliminate both dead cases and dead defaults
; within a single run of simplifycfg
define void @test7(i8 %a) {
-; CHECK-LABEL: @test7(
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[A:%.*]], -2
+; CHECK-LABEL: define void @test7(
+; CHECK-SAME: i8 [[A:%.*]]) {
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[A]], -2
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], -2
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], 1
>From f1aec25fa6b58251de0d8ad2e3509737a7179cad Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Mon, 1 Jan 2024 06:17:54 -0800
Subject: [PATCH 5/7] [MC,test] Improve RISCV/fixups-expr.s
---
llvm/test/MC/RISCV/fixups-expr.s | 34 +++++++++++++++++---------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/llvm/test/MC/RISCV/fixups-expr.s b/llvm/test/MC/RISCV/fixups-expr.s
index 20e5aacac61928..8a02d29de1ab5e 100644
--- a/llvm/test/MC/RISCV/fixups-expr.s
+++ b/llvm/test/MC/RISCV/fixups-expr.s
@@ -31,19 +31,21 @@ G2:
.half G2-G1
.byte .L2-.L1
.byte G2-G1
-# RELAX: 0x0 R_RISCV_ADD64 .L2 0x0
-# RELAX: 0x0 R_RISCV_SUB64 .L1 0x0
-# RELAX: 0x8 R_RISCV_ADD64 G2 0x0
-# RELAX: 0x8 R_RISCV_SUB64 G1 0x0
-# RELAX: 0x10 R_RISCV_ADD32 .L2 0x0
-# RELAX: 0x10 R_RISCV_SUB32 .L1 0x0
-# RELAX: 0x14 R_RISCV_ADD32 G2 0x0
-# RELAX: 0x14 R_RISCV_SUB32 G1 0x0
-# RELAX: 0x18 R_RISCV_ADD16 .L2 0x0
-# RELAX: 0x18 R_RISCV_SUB16 .L1 0x0
-# RELAX: 0x1A R_RISCV_ADD16 G2 0x0
-# RELAX: 0x1A R_RISCV_SUB16 G1 0x0
-# RELAX: 0x1C R_RISCV_ADD8 .L2 0x0
-# RELAX: 0x1C R_RISCV_SUB8 .L1 0x0
-# RELAX: 0x1D R_RISCV_ADD8 G2 0x0
-# RELAX: 0x1D R_RISCV_SUB8 G1 0x0
+# RELAX: .rela.data {
+# RELAX-NEXT: 0x0 R_RISCV_ADD64 .L2 0x0
+# RELAX-NEXT: 0x0 R_RISCV_SUB64 .L1 0x0
+# RELAX-NEXT: 0x8 R_RISCV_ADD64 G2 0x0
+# RELAX-NEXT: 0x8 R_RISCV_SUB64 G1 0x0
+# RELAX-NEXT: 0x10 R_RISCV_ADD32 .L2 0x0
+# RELAX-NEXT: 0x10 R_RISCV_SUB32 .L1 0x0
+# RELAX-NEXT: 0x14 R_RISCV_ADD32 G2 0x0
+# RELAX-NEXT: 0x14 R_RISCV_SUB32 G1 0x0
+# RELAX-NEXT: 0x18 R_RISCV_ADD16 .L2 0x0
+# RELAX-NEXT: 0x18 R_RISCV_SUB16 .L1 0x0
+# RELAX-NEXT: 0x1A R_RISCV_ADD16 G2 0x0
+# RELAX-NEXT: 0x1A R_RISCV_SUB16 G1 0x0
+# RELAX-NEXT: 0x1C R_RISCV_ADD8 .L2 0x0
+# RELAX-NEXT: 0x1C R_RISCV_SUB8 .L1 0x0
+# RELAX-NEXT: 0x1D R_RISCV_ADD8 G2 0x0
+# RELAX-NEXT: 0x1D R_RISCV_SUB8 G1 0x0
+# RELAX-NEXT: }
>From 88c1c60d593b33699b9ff630e2db8bfbde52eba0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 25 Dec 2023 09:49:05 +0700
Subject: [PATCH 6/7] AMDGPU: Add more select bf16 vector tests
---
llvm/test/CodeGen/AMDGPU/bf16.ll | 4760 ++++++++++++++++++++++++++++++
1 file changed, 4760 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 85a24a063aa4e1..adc23860e8965d 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -26957,6 +26957,4766 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
ret i32 %readlane
}
+define <3 x bfloat> @v_select_v3bf16(i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b) {
+; GCN-LABEL: v_select_v3bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_select_v3bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_select_v3bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_select_v3bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_select_v3bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v3bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b
+ ret <3 x bfloat> %op
+}
+
+define <4 x bfloat> @v_select_v4bf16(i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b) {
+; GCN-LABEL: v_select_v4bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_select_v4bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_select_v4bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_select_v4bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_select_v4bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v6, v5 :: v_dual_cndmask_b32 v0, v7, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v3
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b
+ ret <4 x bfloat> %op
+}
+
+define <6 x bfloat> @v_select_v6bf16(i1 %cond, <6 x bfloat> %a, <6 x bfloat> %b) {
+; GCN-LABEL: v_select_v6bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_select_v6bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_select_v6bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v12, v11, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_select_v6bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v12, v11, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_select_v6bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v9, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v11, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v6bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v6
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v5, v2 :: v_dual_cndmask_b32 v5, v10, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v7 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select i1 %cond, <6 x bfloat> %a, <6 x bfloat> %b
+ ret <6 x bfloat> %op
+}
+
+define <8 x bfloat> @v_select_v8bf16(i1 %cond, <8 x bfloat> %a, <8 x bfloat> %b) {
+; GCN-LABEL: v_select_v8bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_select_v8bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_select_v8bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v15, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v12, v11, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v14, v13, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_select_v8bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v12, v11, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v14, v13, vcc
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v16, v15, vcc
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v8
+; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_select_v8bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v8
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v13, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v15, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v8bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX11-NEXT: v_dual_cndmask_b32 v13, v7, v3 :: v_dual_cndmask_b32 v4, v8, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v10, v9 :: v_dual_and_b32 v4, 0xffff, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_and_b32 v1, 0xffff, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v11 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_and_b32 v12, 0xffff, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v5
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v2, v12, v3
+; GFX11-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select i1 %cond, <8 x bfloat> %a, <8 x bfloat> %b
+ ret <8 x bfloat> %op
+}
+
+define <16 x bfloat> @v_select_v16bf16(i1 %cond, <16 x bfloat> %a, <16 x bfloat> %b) {
+; GCN-LABEL: v_select_v16bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v14
+; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v30
+; GCN-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v13
+; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v29
+; GCN-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v28
+; GCN-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v11
+; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v27
+; GCN-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v26
+; GCN-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v25
+; GCN-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v24
+; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v23
+; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v22
+; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v21
+; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4
+; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v20
+; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
+; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s32
+; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v17
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v18
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v19
+; GCN-NEXT: v_cndmask_b32_e32 v3, v18, v3, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v17, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v10
+; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v14
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v21
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v20
+; GCN-NEXT: v_cndmask_b32_e32 v16, v14, v16, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v14, v17, v15, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v16
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_select_v16bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v14
+; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v30
+; GFX7-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v13
+; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v29
+; GFX7-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v28
+; GFX7-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v11
+; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v27
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v26
+; GFX7-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v25
+; GFX7-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v24
+; GFX7-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v23
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v22
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v21
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX7-NEXT: buffer_load_dword v20, off, s[0:3], s32
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX7-NEXT: s_waitcnt vmcnt(1)
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v16, v0, v16, vcc
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v18, 16, v20
+; GFX7-NEXT: v_cndmask_b32_e32 v15, v18, v15, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 16, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GFX7-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 16, v14
+; GFX7-NEXT: v_lshlrev_b32_e32 v14, 16, v15
+; GFX7-NEXT: v_lshlrev_b32_e32 v15, 16, v16
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_select_v16bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v8
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v20, v0, v20, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v15
+; GFX8-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v14
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v11
+; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v0, v19, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v17, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v11
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; GFX8-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v16
+; GFX8-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; GFX8-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_select_v16bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v8
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v16
+; GFX9-NEXT: v_cndmask_b32_e32 v20, v0, v20, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v15
+; GFX9-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v14
+; GFX9-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v13
+; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v11
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v0, v19, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v18, v17, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v11
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v16
+; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_select_v16bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v7
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v15
+; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v12
+; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v13
+; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v8
+; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v16
+; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v6
+; GFX10-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v16, v0, v27, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v22, v21, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v18, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v17, v20, v19, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v28, v29, v28, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v31, v30, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v26, v25, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v17
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v24, v23, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v14
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v16
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; GFX10-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v4, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v5, v6, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v6, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v7, v8, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v16bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v2
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v16, v0, v27 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v18, v17, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v23, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v24, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_and_b32 v1, 0xffff, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v10, v20, v19 :: v_dual_lshlrev_b32 v9, 16, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v22, v21, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v28, v29, v28 :: v_dual_cndmask_b32 v15, v31, v30
+; GFX11-NEXT: v_dual_cndmask_b32 v14, v26, v25 :: v_dual_and_b32 v3, 0xffff, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_and_b32 v2, 0xffff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_dual_cndmask_b32 v12, v24, v23 :: v_dual_lshlrev_b32 v11, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v11
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v15
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v16
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-NEXT: v_or_b32_e32 v4, v5, v9
+; GFX11-NEXT: v_or_b32_e32 v5, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v6, v7, v11
+; GFX11-NEXT: v_or_b32_e32 v7, v8, v12
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select i1 %cond, <16 x bfloat> %a, <16 x bfloat> %b
+ ret <16 x bfloat> %op
+}
+
+define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat> %b) {
+; GCN-LABEL: v_select_v32bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:128
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_cndmask_b32_e32 v31, v0, v31, vcc
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v32
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v33
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:124
+; GCN-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v30
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:120
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v29
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:116
+; GCN-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v28
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:112
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:108
+; GCN-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:104
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:100
+; GCN-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:96
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:92
+; GCN-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:88
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v22, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v21
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84
+; GCN-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v20
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v20, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v19
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:76
+; GCN-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v18
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:72
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v18, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v18, v18, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v17
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
+; GCN-NEXT: v_cndmask_b32_e32 v17, v17, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v16
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v16, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v15
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v34
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:60
+; GCN-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v14
+; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; GCN-NEXT: v_cndmask_b32_e32 v33, v33, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v13
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v14
+; GCN-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:52
+; GCN-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; GCN-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v11
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v12
+; GCN-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:44
+; GCN-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:40
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GCN-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v10
+; GCN-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:36
+; GCN-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GCN-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v8
+; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
+; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v6
+; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:20
+; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v4
+; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12
+; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v8
+; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v10
+; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v12
+; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v14
+; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v33
+; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v15
+; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v16
+; GCN-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v20
+; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v22
+; GCN-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v25
+; GCN-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GCN-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GCN-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GCN-NEXT: v_lshlrev_b32_e32 v28, 16, v29
+; GCN-NEXT: v_lshlrev_b32_e32 v29, 16, v30
+; GCN-NEXT: v_lshlrev_b32_e32 v30, 16, v32
+; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_select_v32bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128
+; GFX7-NEXT: s_waitcnt vmcnt(2)
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: s_waitcnt vmcnt(1)
+; GFX7-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; GFX7-NEXT: v_cndmask_b32_e32 v31, v31, v0, vcc
+; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32
+; GFX7-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX7-NEXT: s_waitcnt vmcnt(1)
+; GFX7-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v30
+; GFX7-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; GFX7-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v29
+; GFX7-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:120
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; GFX7-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v28
+; GFX7-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:116
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; GFX7-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v27
+; GFX7-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; GFX7-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v26
+; GFX7-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:108
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; GFX7-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v25
+; GFX7-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; GFX7-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; GFX7-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; GFX7-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v23
+; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; GFX7-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v22
+; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; GFX7-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v21
+; GFX7-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; GFX7-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v20
+; GFX7-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; GFX7-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v19
+; GFX7-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; GFX7-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v18
+; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v17
+; GFX7-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v16
+; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX7-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v15
+; GFX7-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX7-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v14
+; GFX7-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; GFX7-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v13
+; GFX7-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX7-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; GFX7-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX7-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v11
+; GFX7-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GFX7-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX7-NEXT: v_cndmask_b32_e32 v10, v10, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; GFX7-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX7-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GFX7-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX7-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX7-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX7-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX7-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX7-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX7-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX7-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX7-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX7-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX7-NEXT: v_lshlrev_b32_e32 v9, 16, v10
+; GFX7-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX7-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GFX7-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GFX7-NEXT: v_lshlrev_b32_e32 v13, 16, v14
+; GFX7-NEXT: v_lshlrev_b32_e32 v14, 16, v15
+; GFX7-NEXT: v_lshlrev_b32_e32 v15, 16, v16
+; GFX7-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; GFX7-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX7-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX7-NEXT: v_lshlrev_b32_e32 v19, 16, v20
+; GFX7-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; GFX7-NEXT: v_lshlrev_b32_e32 v21, 16, v22
+; GFX7-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GFX7-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX7-NEXT: v_lshlrev_b32_e32 v24, 16, v25
+; GFX7-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX7-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX7-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX7-NEXT: v_lshlrev_b32_e32 v28, 16, v29
+; GFX7-NEXT: v_lshlrev_b32_e32 v29, 16, v30
+; GFX7-NEXT: v_lshlrev_b32_e32 v30, 16, v32
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_select_v32bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v29
+; GFX8-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; GFX8-NEXT: v_lshrrev_b32_e32 v29, 16, v28
+; GFX8-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v11
+; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v27
+; GFX8-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v26
+; GFX8-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v25
+; GFX8-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24
+; GFX8-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v23
+; GFX8-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v22
+; GFX8-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v21
+; GFX8-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc
+; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v20
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_cndmask_b32_e32 v16, v0, v16, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v33, v0, v33, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v15
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v32, v15, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v19
+; GFX8-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v17
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v21
+; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; GFX8-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v24
+; GFX8-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v25
+; GFX8-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; GFX8-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; GFX8-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v28
+; GFX8-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v29
+; GFX8-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v30
+; GFX8-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; GFX8-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v32
+; GFX8-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v33
+; GFX8-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_select_v32bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; GFX9-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v13
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v29
+; GFX9-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v28
+; GFX9-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v11
+; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v27
+; GFX9-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v26
+; GFX9-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v25
+; GFX9-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v24
+; GFX9-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
+; GFX9-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v22
+; GFX9-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v21
+; GFX9-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v16
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v20
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_cndmask_b32_e32 v16, v0, v16, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v33, v0, v33, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e32 v15, v32, v15, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; GFX9-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v19
+; GFX9-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v18
+; GFX9-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v17
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
+; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v24
+; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v25
+; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v28
+; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v29
+; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v30
+; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v32
+; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v33
+; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_select_v32bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v13
+; GFX10-NEXT: v_lshrrev_b32_e32 v68, 16, v29
+; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v18
+; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v14
+; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v30
+; GFX10-NEXT: v_cndmask_b32_e32 v67, v68, v67, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v68, 16, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v19
+; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v20
+; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v21
+; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v6
+; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v22
+; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v8
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v24
+; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v64, v65, v64, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v28
+; GFX10-NEXT: v_cndmask_b32_e32 v29, v29, v68, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v68, 16, v25
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v25, v34, v33, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v33, v36, v35, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v30, v30, v65, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v10
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v26
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v55, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v24, v54, v53, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v23, v52, v51, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v22, v50, v49, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v21, v48, v39, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v20, v38, v37, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v25
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v33
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v16
+; GFX10-NEXT: v_cndmask_b32_e32 v28, v28, v65, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v15
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v20
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v22
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v0
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v26, v68, v66, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v64
+; GFX10-NEXT: v_or_b32_sdwa v2, v3, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v4, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v4, v5, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v67
+; GFX10-NEXT: v_or_b32_sdwa v5, v6, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v6, v7, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v7, v8, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v8, v9, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v9, v10, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v10, v11, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v11, v12, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v12, v13, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v13, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v31
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v32
+; GFX10-NEXT: v_cndmask_b32_e32 v16, v32, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v31, v15, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v65, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v27, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX10-NEXT: v_or_b32_sdwa v14, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v15, v16, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v32bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: scratch_load_b32 v31, off, s32 offset:4
+; GFX11-NEXT: scratch_load_b32 v32, off, s32
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v65, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v83, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v16
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v30
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v30, v82, v81 :: v_dual_cndmask_b32 v11, v27, v11
+; GFX11-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX11-NEXT: v_dual_cndmask_b32 v28, v70, v69 :: v_dual_cndmask_b32 v27, v68, v67
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v26, v66, v65 :: v_dual_cndmask_b32 v23, v52, v51
+; GFX11-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v5, v21, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v24, v54, v53 :: v_dual_cndmask_b32 v21, v48, v39
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v22, v50, v49 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v17, v34, v33
+; GFX11-NEXT: v_cndmask_b32_e32 v20, v38, v37, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_and_b32 v1, 0xffff, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v18, v36, v35 :: v_dual_lshlrev_b32 v17, 16, v17
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v22
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-NEXT: v_dual_cndmask_b32 v13, v29, v13 :: v_dual_and_b32 v12, 0xffff, v12
+; GFX11-NEXT: v_dual_cndmask_b32 v29, v80, v71 :: v_dual_and_b32 v14, 0xffff, v14
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v25, v64, v55 :: v_dual_and_b32 v10, 0xffff, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v29
+; GFX11-NEXT: v_lshlrev_b32_e32 v29, 16, v30
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v31
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v32
+; GFX11-NEXT: v_dual_cndmask_b32 v16, v31, v16 :: v_dual_cndmask_b32 v15, v32, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v31, v87, v86 :: v_dual_cndmask_b32 v84, v85, v84
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v83, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshlrev_b32_e32 v30, 16, v31
+; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v84
+; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v17
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v18
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v19
+; GFX11-NEXT: v_or_b32_e32 v3, v4, v20
+; GFX11-NEXT: v_or_b32_e32 v4, v5, v21
+; GFX11-NEXT: v_or_b32_e32 v5, v6, v22
+; GFX11-NEXT: v_or_b32_e32 v6, v7, v23
+; GFX11-NEXT: v_or_b32_e32 v7, v8, v24
+; GFX11-NEXT: v_or_b32_e32 v8, v9, v25
+; GFX11-NEXT: v_or_b32_e32 v9, v10, v26
+; GFX11-NEXT: v_or_b32_e32 v10, v11, v27
+; GFX11-NEXT: v_or_b32_e32 v11, v12, v28
+; GFX11-NEXT: v_or_b32_e32 v12, v13, v29
+; GFX11-NEXT: v_or_b32_e32 v13, v14, v30
+; GFX11-NEXT: v_or_b32_e32 v14, v15, v31
+; GFX11-NEXT: v_or_b32_e32 v15, v16, v32
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select i1 %cond, <32 x bfloat> %a, <32 x bfloat> %b
+ ret <32 x bfloat> %op
+}
+
+define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat> inreg %b, i32 %c) {
+; GCN-LABEL: s_select_v3bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshr_b32 s2, s2, 16
+; GCN-NEXT: s_lshr_b32 s5, s5, 16
+; GCN-NEXT: s_lshr_b32 s1, s1, 16
+; GCN-NEXT: s_lshr_b32 s0, s0, 16
+; GCN-NEXT: s_lshr_b32 s3, s3, 16
+; GCN-NEXT: s_lshr_b32 s4, s4, 16
+; GCN-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, s4
+; GCN-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: v_readfirstlane_b32 s1, v2
+; GCN-NEXT: ; return to shader part epilog
+;
+; GFX7-LABEL: s_select_v3bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_lshr_b32 s0, s0, 16
+; GFX7-NEXT: s_lshr_b32 s3, s3, 16
+; GFX7-NEXT: s_lshr_b32 s1, s1, 16
+; GFX7-NEXT: s_lshr_b32 s4, s4, 16
+; GFX7-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: s_lshr_b32 s2, s2, 16
+; GFX7-NEXT: s_lshr_b32 s5, s5, 16
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_readfirstlane_b32 s0, v0
+; GFX7-NEXT: v_readfirstlane_b32 s1, v1
+; GFX7-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: s_select_v3bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_lshr_b32 s4, s0, 16
+; GFX8-NEXT: s_lshr_b32 s5, s2, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: s_select_v3bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshr_b32 s4, s0, 16
+; GFX9-NEXT: s_lshr_b32 s5, s2, 16
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: s_select_v3bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_lshr_b32 s4, s0, 16
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_mov_b32_e32 v1, s4
+; GFX10-NEXT: s_lshr_b32 s4, s2, 16
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, s4, v1, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, s2, v2, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
+; GFX10-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_select_v3bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s4, s0, 16
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_lshr_b32 s5, s2, 16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, s5, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_cndmask_b32 v1, s2, v2 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_and_b32 v1, 0xffff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, s3, v2, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: ; return to shader part epilog
+ %cond = icmp eq i32 %c, 0
+ %op = select i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b
+ %cast = bitcast <3 x bfloat> %op to i48
+ %elt0 = trunc i48 %cast to i32
+ %elt1.hi = lshr i48 %cast, 32
+ %elt1 = trunc i48 %elt1.hi to i32
+ %readlane0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt0)
+ %readlane1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt1)
+ %bv.0 = insertelement <2 x i32> poison, i32 %readlane0, i32 0
+ %bv.1 = insertelement <2 x i32> %bv.0, i32 %readlane1, i32 1
+ ret <2 x i32> %bv.1
+}
+
+define amdgpu_ps <2 x i32> @s_select_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat> inreg %b, i32 %c) {
+; GCN-LABEL: s_select_v4bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshr_b32 s1, s1, 16
+; GCN-NEXT: s_lshr_b32 s5, s5, 16
+; GCN-NEXT: s_lshr_b32 s0, s0, 16
+; GCN-NEXT: s_lshr_b32 s4, s4, 16
+; GCN-NEXT: s_lshr_b32 s3, s3, 16
+; GCN-NEXT: s_lshr_b32 s2, s2, 16
+; GCN-NEXT: s_lshr_b32 s6, s6, 16
+; GCN-NEXT: s_lshr_b32 s7, s7, 16
+; GCN-NEXT: v_mov_b32_e32 v1, s6
+; GCN-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GCN-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: v_mov_b32_e32 v3, s4
+; GCN-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NEXT: v_mov_b32_e32 v6, s1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: v_or_b32_e32 v1, v2, v3
+; GCN-NEXT: v_readfirstlane_b32 s0, v1
+; GCN-NEXT: v_readfirstlane_b32 s1, v0
+; GCN-NEXT: ; return to shader part epilog
+;
+; GFX7-LABEL: s_select_v4bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_lshr_b32 s2, s2, 16
+; GFX7-NEXT: s_lshr_b32 s6, s6, 16
+; GFX7-NEXT: s_lshr_b32 s3, s3, 16
+; GFX7-NEXT: s_lshr_b32 s7, s7, 16
+; GFX7-NEXT: v_mov_b32_e32 v1, s6
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: s_lshr_b32 s0, s0, 16
+; GFX7-NEXT: s_lshr_b32 s4, s4, 16
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT: s_lshr_b32 s1, s1, 16
+; GFX7-NEXT: s_lshr_b32 s5, s5, 16
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX7-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX7-NEXT: v_readfirstlane_b32 s0, v1
+; GFX7-NEXT: v_readfirstlane_b32 s1, v0
+; GFX7-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: s_select_v4bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_lshr_b32 s6, s1, 16
+; GFX8-NEXT: s_lshr_b32 s7, s3, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_lshr_b32 s4, s0, 16
+; GFX8-NEXT: s_lshr_b32 s5, s2, 16
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: s_select_v4bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshr_b32 s6, s1, 16
+; GFX9-NEXT: s_lshr_b32 s7, s3, 16
+; GFX9-NEXT: v_mov_b32_e32 v1, s7
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: s_lshr_b32 s4, s0, 16
+; GFX9-NEXT: s_lshr_b32 s5, s2, 16
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_mov_b32_e32 v3, s0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_readfirstlane_b32 s0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: s_select_v4bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_lshr_b32 s4, s0, 16
+; GFX10-NEXT: s_lshr_b32 s5, s1, 16
+; GFX10-NEXT: v_mov_b32_e32 v2, s4
+; GFX10-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: s_lshr_b32 s6, s3, 16
+; GFX10-NEXT: s_lshr_b32 s4, s2, 16
+; GFX10-NEXT: v_mov_b32_e32 v3, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, s6, v1, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, s4, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, s2, v3, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_readfirstlane_b32 s1, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v2
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_select_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s4, s0, 16
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: s_lshr_b32 s6, s3, 16
+; GFX11-NEXT: s_lshr_b32 s0, s2, 16
+; GFX11-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v3, s3, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: ; return to shader part epilog
+ %cond = icmp eq i32 %c, 0
+ %op = select i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b
+ %cast = bitcast <4 x bfloat> %op to <2 x i32>
+ %elt0 = extractelement <2 x i32> %cast, i32 0
+ %elt1 = extractelement <2 x i32> %cast, i32 1
+ %readlane0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt0)
+ %readlane1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt1)
+ %bv.0 = insertelement <2 x i32> poison, i32 %readlane0, i32 0
+ %bv.1 = insertelement <2 x i32> %bv.0, i32 %readlane1, i32 1
+ ret <2 x i32> %bv.1
+}
+
+define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat> inreg %b, <4 x i32> %c) {
+; GCN-LABEL: s_vselect_v4bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v4, s7
+; GCN-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GCN-NEXT: v_mov_b32_e32 v4, s6
+; GCN-NEXT: v_mov_b32_e32 v5, s2
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; GCN-NEXT: v_mov_b32_e32 v4, s5
+; GCN-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; GCN-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NEXT: v_mov_b32_e32 v5, s0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GCN-NEXT: v_or_b32_e32 v2, v2, v3
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: v_readfirstlane_b32 s0, v0
+; GCN-NEXT: v_readfirstlane_b32 s1, v2
+; GCN-NEXT: ; return to shader part epilog
+;
+; GFX7-LABEL: s_vselect_v4bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: v_mov_b32_e32 v4, s7
+; GFX7-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX7-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-NEXT: v_mov_b32_e32 v5, s2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT: v_mov_b32_e32 v3, s5
+; GFX7-NEXT: v_mov_b32_e32 v4, s1
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX7-NEXT: v_mov_b32_e32 v3, s4
+; GFX7-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_readfirstlane_b32 s0, v0
+; GFX7-NEXT: v_readfirstlane_b32 s1, v2
+; GFX7-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: s_vselect_v4bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_lshr_b32 s6, s1, 16
+; GFX8-NEXT: s_lshr_b32 s7, s3, 16
+; GFX8-NEXT: v_mov_b32_e32 v4, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX8-NEXT: s_lshr_b32 s4, s0, 16
+; GFX8-NEXT: s_lshr_b32 s5, s2, 16
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v2
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: s_vselect_v4bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_lshr_b32 s6, s1, 16
+; GFX9-NEXT: s_lshr_b32 s7, s3, 16
+; GFX9-NEXT: v_mov_b32_e32 v4, s7
+; GFX9-NEXT: v_mov_b32_e32 v5, s6
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, s3
+; GFX9-NEXT: v_mov_b32_e32 v5, s1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX9-NEXT: s_lshr_b32 s4, s0, 16
+; GFX9-NEXT: s_lshr_b32 s5, s2, 16
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_mov_b32_e32 v4, s0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v2
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: s_vselect_v4bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_lshr_b32 s4, s1, 16
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: s_lshr_b32 s5, s0, 16
+; GFX10-NEXT: s_lshr_b32 s4, s2, 16
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: s_lshr_b32 s5, s3, 16
+; GFX10-NEXT: v_cndmask_b32_e32 v3, s5, v4, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-NEXT: v_mov_b32_e32 v4, s0
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v5, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_mov_b32_e32 v5, s1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, s2, v4, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_cndmask_b32_e32 v2, s3, v5, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_vselect_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s4, s1, 16
+; GFX11-NEXT: s_lshr_b32 s5, s0, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3
+; GFX11-NEXT: s_lshr_b32 s6, s3, 16
+; GFX11-NEXT: s_lshr_b32 s4, s2, 16
+; GFX11-NEXT: v_cndmask_b32_e32 v3, s6, v4, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, s4, v5, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_dual_mov_b32 v6, s1 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, s2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, s3, v6, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: ; return to shader part epilog
+ %cond = icmp eq <4 x i32> %c, zeroinitializer
+ %op = select <4 x i1> %cond, <4 x bfloat> %a, <4 x bfloat> %b
+ %cast = bitcast <4 x bfloat> %op to <2 x i32>
+ %elt0 = extractelement <2 x i32> %cast, i32 0
+ %elt1 = extractelement <2 x i32> %cast, i32 1
+ %readlane0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt0)
+ %readlane1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt1)
+ %bv.0 = insertelement <2 x i32> poison, i32 %readlane0, i32 0
+ %bv.1 = insertelement <2 x i32> %bv.0, i32 %readlane1, i32 1
+ ret <2 x i32> %bv.1
+}
+
+define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bfloat> %b) {
+; GCN-LABEL: v_vselect_v4bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_and_b32_e32 v1, 1, v1
+; GCN-NEXT: v_and_b32_e32 v2, 1, v2
+; GCN-NEXT: v_and_b32_e32 v3, 1, v3
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v7, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v6, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v5, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_vselect_v4bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX7-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v11, v7, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v10, v6, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v9, v5, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_vselect_v4bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_vselect_v4bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v10, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_vselect_v4bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
+; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v4bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v7, v5 :: v_dual_and_b32 v3, 1, v3
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v10, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select <4 x i1> %cond, <4 x bfloat> %a, <4 x bfloat> %b
+ ret <4 x bfloat> %op
+}
+
+define <8 x bfloat> @v_vselect_v8bf16(<8 x i1> %cond, <8 x bfloat> %a, <8 x bfloat> %b) {
+; GCN-LABEL: v_vselect_v8bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_and_b32_e32 v1, 1, v1
+; GCN-NEXT: v_and_b32_e32 v2, 1, v2
+; GCN-NEXT: v_and_b32_e32 v3, 1, v3
+; GCN-NEXT: v_and_b32_e32 v4, 1, v4
+; GCN-NEXT: v_and_b32_e32 v5, 1, v5
+; GCN-NEXT: v_and_b32_e32 v6, 1, v6
+; GCN-NEXT: v_and_b32_e32 v7, 1, v7
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GCN-NEXT: v_cndmask_b32_e32 v7, v23, v15, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GCN-NEXT: v_cndmask_b32_e32 v6, v22, v14, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GCN-NEXT: v_cndmask_b32_e32 v5, v21, v13, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GCN-NEXT: v_cndmask_b32_e32 v4, v20, v12, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v19, v11, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v18, v10, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v17, v9, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v16, v8, vcc
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_vselect_v8bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX7-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX7-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v23, v15, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX7-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v22, v14, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX7-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v21, v13, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX7-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v20, v12, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v19, v11, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v18, v10, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v17, v9, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v16, v8, vcc
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_vselect_v8bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v15
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v23, v22, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v14
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v21, v20, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v13
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_vselect_v8bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX9-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v15
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX9-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v23, v22, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v14
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v21, v20, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v13
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v18, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v12
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX9-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_vselect_v8bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v15
+; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v13
+; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v23, v22, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v12
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v20, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v18, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc_lo
+; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v8bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v23, 16, v15
+; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v23, v22 :: v_dual_and_b32 v4, 0xffff, v4
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v13, v9 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v18, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v12, v8 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v21, v20, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select <8 x i1> %cond, <8 x bfloat> %a, <8 x bfloat> %b
+ ret <8 x bfloat> %op
+}
+
+define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x bfloat> %b) {
+; GCN-LABEL: v_vselect_v16bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_waitcnt expcnt(0)
+; GCN-NEXT: v_writelane_b32 v31, s30, 0
+; GCN-NEXT: v_writelane_b32 v31, s31, 1
+; GCN-NEXT: v_writelane_b32 v31, s34, 2
+; GCN-NEXT: v_writelane_b32 v31, s35, 3
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v1
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v2
+; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v3
+; GCN-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v4
+; GCN-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v5
+; GCN-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v6
+; GCN-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v7
+; GCN-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v8
+; GCN-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v9
+; GCN-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0
+; GCN-NEXT: v_and_b32_e32 v0, 1, v10
+; GCN-NEXT: v_and_b32_e32 v1, 1, v11
+; GCN-NEXT: v_and_b32_e32 v2, 1, v12
+; GCN-NEXT: v_and_b32_e32 v3, 1, v13
+; GCN-NEXT: v_and_b32_e32 v4, 1, v14
+; GCN-NEXT: v_and_b32_e32 v5, 1, v15
+; GCN-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0
+; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GCN-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v1
+; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12
+; GCN-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v2
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32
+; GCN-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v3
+; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64
+; GCN-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v4
+; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60
+; GCN-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v5
+; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:56
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v15, v3, v2, s[34:35]
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:52
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v14, v4, v30, s[30:31]
+; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:48
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v13, v5, v29, s[28:29]
+; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:44
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v12, v2, v28, s[26:27]
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v11, v3, v27, s[24:25]
+; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:36
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v10, v4, v26, s[22:23]
+; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v9, v2, v25, s[20:21]
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:28
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v8, v3, v24, s[18:19]
+; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:24
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v7, v4, v23, s[16:17]
+; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v6, v2, v22, s[14:15]
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v5, v3, v21, s[12:13]
+; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v20, s[10:11]
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_cndmask_b32_e64 v19, v2, v19, s[8:9]
+; GCN-NEXT: v_cndmask_b32_e64 v2, v1, v18, s[6:7]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v17, s[4:5]
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v19
+; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GCN-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GCN-NEXT: v_readlane_b32 s35, v31, 3
+; GCN-NEXT: v_readlane_b32 s34, v31, 2
+; GCN-NEXT: v_readlane_b32 s31, v31, 1
+; GCN-NEXT: v_readlane_b32 s30, v31, 0
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_vselect_v16bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GFX7-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX7-NEXT: s_mov_b64 exec, s[4:5]
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v1
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v3
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v4
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v5
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v6
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v7
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v8
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v9
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v10
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v11
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v12
+; GFX7-NEXT: v_writelane_b32 v31, s30, 0
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v13
+; GFX7-NEXT: v_writelane_b32 v31, s31, 1
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v14
+; GFX7-NEXT: v_writelane_b32 v31, s34, 2
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v15
+; GFX7-NEXT: v_writelane_b32 v31, s35, 3
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0
+; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GFX7-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; GFX7-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12
+; GFX7-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16
+; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20
+; GFX7-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24
+; GFX7-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28
+; GFX7-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32
+; GFX7-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
+; GFX7-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40
+; GFX7-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44
+; GFX7-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48
+; GFX7-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
+; GFX7-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56
+; GFX7-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60
+; GFX7-NEXT: buffer_load_dword v15, off, s[0:3], s32
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
+; GFX7-NEXT: s_waitcnt vmcnt(14)
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[6:7]
+; GFX7-NEXT: s_waitcnt vmcnt(13)
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[8:9]
+; GFX7-NEXT: s_waitcnt vmcnt(12)
+; GFX7-NEXT: v_cndmask_b32_e64 v4, v4, v20, s[10:11]
+; GFX7-NEXT: s_waitcnt vmcnt(11)
+; GFX7-NEXT: v_cndmask_b32_e64 v5, v5, v21, s[12:13]
+; GFX7-NEXT: s_waitcnt vmcnt(10)
+; GFX7-NEXT: v_cndmask_b32_e64 v6, v6, v22, s[14:15]
+; GFX7-NEXT: s_waitcnt vmcnt(9)
+; GFX7-NEXT: v_cndmask_b32_e64 v7, v7, v23, s[16:17]
+; GFX7-NEXT: s_waitcnt vmcnt(8)
+; GFX7-NEXT: v_cndmask_b32_e64 v8, v8, v24, s[18:19]
+; GFX7-NEXT: s_waitcnt vmcnt(7)
+; GFX7-NEXT: v_cndmask_b32_e64 v9, v9, v25, s[20:21]
+; GFX7-NEXT: s_waitcnt vmcnt(6)
+; GFX7-NEXT: v_cndmask_b32_e64 v10, v10, v26, s[22:23]
+; GFX7-NEXT: s_waitcnt vmcnt(5)
+; GFX7-NEXT: v_cndmask_b32_e64 v11, v11, v27, s[24:25]
+; GFX7-NEXT: s_waitcnt vmcnt(4)
+; GFX7-NEXT: v_cndmask_b32_e64 v12, v12, v28, s[26:27]
+; GFX7-NEXT: s_waitcnt vmcnt(3)
+; GFX7-NEXT: v_cndmask_b32_e64 v13, v13, v29, s[28:29]
+; GFX7-NEXT: s_waitcnt vmcnt(2)
+; GFX7-NEXT: v_cndmask_b32_e64 v14, v14, v30, s[30:31]
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e64 v15, v32, v15, s[34:35]
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX7-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX7-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX7-NEXT: v_readlane_b32 s35, v31, 3
+; GFX7-NEXT: v_readlane_b32 s34, v31, 2
+; GFX7-NEXT: v_readlane_b32 s31, v31, 1
+; GFX7-NEXT: v_readlane_b32 s30, v31, 0
+; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; GFX7-NEXT: s_mov_b64 exec, s[4:5]
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_vselect_v16bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v31, 16, v22
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v32, v31, vcc
+; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX8-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v21
+; GFX8-NEXT: v_cndmask_b32_e32 v22, v30, v22, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v29
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v11
+; GFX8-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v20
+; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v28
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v21, v29, v21, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v30, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v19
+; GFX8-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v20, v28, v20, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v29, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v18
+; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v26
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v30, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX8-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v14
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v23
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v17
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v24
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v31, v23, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v31
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v25
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v10, v28, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v14, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX8-NEXT: v_or_b32_sdwa v4, v20, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v5, v21, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v6, v22, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v7, v9, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_vselect_v16bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v22
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v13
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v32, v31, vcc
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; GFX9-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX9-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v21
+; GFX9-NEXT: v_cndmask_b32_e32 v22, v30, v22, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v29
+; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v11
+; GFX9-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v30, v12, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v20
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v28
+; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v21, v29, v21, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX9-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v30, v11, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v19
+; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v27
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v20, v28, v20, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX9-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v29, v10, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v18
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v26
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX9-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v30, v9, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX9-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v14
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v23
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v17
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v24
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v31, v23, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v31
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v25
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v10, v28, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v16
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v14, v10, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX9-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX9-NEXT: v_or_b32_sdwa v4, v20, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v5, v21, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v6, v22, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v7, v9, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_vselect_v16bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; GFX10-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v22
+; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v30
+; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX10-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v21
+; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v29
+; GFX10-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX10-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v53, v52, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v20
+; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v28
+; GFX10-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v22, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
+; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v19
+; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v27
+; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v51, v50, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v18
+; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v26
+; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v25
+; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v16
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v49, v48, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
+; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v24
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; GFX10-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v39, v38, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v37, v36, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v35, v34, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
+; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v4, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v5, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v6, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v31
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v54, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v31, v23, vcc_lo
+; GFX10-NEXT: v_or_b32_sdwa v7, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v16bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; GFX11-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v26
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v53, v52, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v29
+; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v30, v22, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v25
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v51, v50, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v28
+; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX11-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v27
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v49, v48, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
+; GFX11-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v24
+; GFX11-NEXT: v_dual_cndmask_b32 v8, v28, v20 :: v_dual_and_b32 v15, 1, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v39, v38 :: v_dual_and_b32 v8, 0xffff, v8
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v37, v36 :: v_dual_and_b32 v6, 0xffff, v6
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v35, v34, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v31, v23, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v31
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v16, v54, vcc_lo
+; GFX11-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
+; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
+; GFX11-NEXT: v_or_b32_e32 v6, v12, v13
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v7, v14, v15
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select <16 x i1> %cond, <16 x bfloat> %a, <16 x bfloat> %b
+ ret <16 x bfloat> %op
+}
+
+define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x bfloat> %b) {
+; GCN-LABEL: v_vselect_v32bf16:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v31, 1, v30
+; GCN-NEXT: v_and_b32_e32 v29, 1, v29
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:124
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:252
+; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:128
+; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:120
+; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:248
+; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:116
+; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:244
+; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:240
+; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:104
+; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232
+; GCN-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:100
+; GCN-NEXT: v_and_b32_e32 v51, 1, v5
+; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24
+; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:152
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v51
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v31
+; GCN-NEXT: s_waitcnt vmcnt(11)
+; GCN-NEXT: v_cndmask_b32_e64 v31, v34, v33, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29
+; GCN-NEXT: s_waitcnt vmcnt(8)
+; GCN-NEXT: v_cndmask_b32_e64 v29, v36, v35, s[4:5]
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:220
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:96
+; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:108
+; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:236
+; GCN-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:112
+; GCN-NEXT: v_and_b32_e32 v18, 1, v18
+; GCN-NEXT: v_and_b32_e32 v22, 1, v22
+; GCN-NEXT: v_and_b32_e32 v26, 1, v26
+; GCN-NEXT: v_and_b32_e32 v28, 1, v28
+; GCN-NEXT: v_and_b32_e32 v27, 1, v27
+; GCN-NEXT: v_and_b32_e32 v25, 1, v25
+; GCN-NEXT: v_and_b32_e32 v24, 1, v24
+; GCN-NEXT: v_and_b32_e32 v23, 1, v23
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v28
+; GCN-NEXT: s_waitcnt vmcnt(11)
+; GCN-NEXT: v_cndmask_b32_e64 v28, v38, v37, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v27
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_cndmask_b32_e64 v27, v39, v51, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v26
+; GCN-NEXT: v_cndmask_b32_e64 v26, v36, v35, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v25
+; GCN-NEXT: v_cndmask_b32_e64 v25, v49, v48, s[4:5]
+; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:228
+; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:224
+; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:88
+; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:216
+; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:84
+; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:212
+; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:208
+; GCN-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:72
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v24
+; GCN-NEXT: s_waitcnt vmcnt(7)
+; GCN-NEXT: v_cndmask_b32_e64 v24, v35, v50, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v23
+; GCN-NEXT: s_waitcnt vmcnt(6)
+; GCN-NEXT: v_cndmask_b32_e64 v23, v36, v34, s[4:5]
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:76
+; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:204
+; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:80
+; GCN-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:92
+; GCN-NEXT: v_and_b32_e32 v21, 1, v21
+; GCN-NEXT: v_and_b32_e32 v20, 1, v20
+; GCN-NEXT: v_and_b32_e32 v19, 1, v19
+; GCN-NEXT: v_and_b32_e32 v17, 1, v17
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v22
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_cndmask_b32_e64 v22, v33, v50, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v21
+; GCN-NEXT: v_cndmask_b32_e64 v21, v38, v37, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v20
+; GCN-NEXT: v_cndmask_b32_e64 v20, v48, v39, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v19
+; GCN-NEXT: v_cndmask_b32_e64 v19, v49, v36, s[4:5]
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:200
+; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68
+; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:196
+; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:192
+; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56
+; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:184
+; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:52
+; GCN-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:180
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v18
+; GCN-NEXT: v_cndmask_b32_e64 v18, v35, v34, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v17
+; GCN-NEXT: s_waitcnt vmcnt(7)
+; GCN-NEXT: v_cndmask_b32_e64 v17, v33, v51, s[4:5]
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:48
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60
+; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:188
+; GCN-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
+; GCN-NEXT: v_and_b32_e32 v14, 1, v14
+; GCN-NEXT: v_and_b32_e32 v16, 1, v16
+; GCN-NEXT: v_and_b32_e32 v15, 1, v15
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v16
+; GCN-NEXT: s_waitcnt vmcnt(9)
+; GCN-NEXT: v_cndmask_b32_e64 v16, v37, v36, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v15
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_cndmask_b32_e64 v15, v38, v51, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v14
+; GCN-NEXT: v_cndmask_b32_e64 v14, v35, v34, s[4:5]
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:176
+; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:40
+; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:168
+; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:36
+; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:164
+; GCN-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:160
+; GCN-NEXT: v_and_b32_e32 v10, 1, v10
+; GCN-NEXT: v_and_b32_e32 v13, 1, v13
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v13
+; GCN-NEXT: v_cndmask_b32_e64 v13, v48, v39, s[4:5]
+; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:44
+; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:172
+; GCN-NEXT: v_and_b32_e32 v12, 1, v12
+; GCN-NEXT: v_and_b32_e32 v11, 1, v11
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v12
+; GCN-NEXT: v_cndmask_b32_e64 v12, v50, v49, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v11
+; GCN-NEXT: s_waitcnt vmcnt(7)
+; GCN-NEXT: v_cndmask_b32_e64 v11, v34, v33, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v10
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_cndmask_b32_e64 v10, v48, v39, s[4:5]
+; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12
+; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:140
+; GCN-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
+; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:28
+; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:156
+; GCN-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
+; GCN-NEXT: v_and_b32_e32 v2, 1, v2
+; GCN-NEXT: v_and_b32_e32 v6, 1, v6
+; GCN-NEXT: v_and_b32_e32 v9, 1, v9
+; GCN-NEXT: v_and_b32_e32 v8, 1, v8
+; GCN-NEXT: v_and_b32_e32 v7, 1, v7
+; GCN-NEXT: v_and_b32_e32 v4, 1, v4
+; GCN-NEXT: v_and_b32_e32 v3, 1, v3
+; GCN-NEXT: v_and_b32_e32 v1, 1, v1
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v9
+; GCN-NEXT: v_cndmask_b32_e64 v9, v36, v35, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v8
+; GCN-NEXT: v_cndmask_b32_e64 v8, v38, v37, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_cndmask_b32_e64 v7, v51, v50, s[4:5]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v6
+; GCN-NEXT: v_cndmask_b32_e64 v6, v49, v48, s[4:5]
+; GCN-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:20
+; GCN-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:148
+; GCN-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:144
+; GCN-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:8
+; GCN-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:136
+; GCN-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:4
+; GCN-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:132
+; GCN-NEXT: buffer_load_dword v51, off, s[0:3], s32
+; GCN-NEXT: v_cndmask_b32_e32 v5, v32, v5, vcc
+; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:256
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GCN-NEXT: s_waitcnt vmcnt(7)
+; GCN-NEXT: v_cndmask_b32_e32 v4, v36, v35, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GCN-NEXT: s_waitcnt vmcnt(6)
+; GCN-NEXT: v_cndmask_b32_e32 v3, v37, v39, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GCN-NEXT: v_cndmask_b32_e32 v2, v34, v33, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GCN-NEXT: s_waitcnt vmcnt(4)
+; GCN-NEXT: v_cndmask_b32_e32 v1, v48, v38, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: v_cndmask_b32_e32 v0, v50, v49, vcc
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_and_b32_e32 v33, 1, v51
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GCN-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GCN-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GCN-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GCN-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GCN-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GCN-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GCN-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GCN-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GCN-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GCN-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GCN-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GCN-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GCN-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GCN-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GCN-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GCN-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GCN-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GCN-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GCN-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GCN-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GCN-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GCN-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GCN-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GCN-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GCN-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GCN-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GCN-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v33
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_cndmask_b32_e32 v32, v32, v30, vcc
+; GCN-NEXT: v_and_b32_e32 v30, 0xffff0000, v31
+; GCN-NEXT: v_and_b32_e32 v31, 0xffff0000, v32
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_vselect_v32bf16:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX7-NEXT: v_and_b32_e32 v27, 1, v27
+; GFX7-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX7-NEXT: v_and_b32_e32 v25, 1, v25
+; GFX7-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX7-NEXT: v_and_b32_e32 v23, 1, v23
+; GFX7-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v28
+; GFX7-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:124
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v27
+; GFX7-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:252
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v26
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v25
+; GFX7-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:248
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v24
+; GFX7-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v23
+; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:244
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v22
+; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:240
+; GFX7-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
+; GFX7-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX7-NEXT: v_and_b32_e32 v29, 1, v29
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v30
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v29
+; GFX7-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX7-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX7-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX7-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX7-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX7-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX7-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX7-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX7-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX7-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX7-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX7-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX7-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX7-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX7-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX7-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX7-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX7-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX7-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX7-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX7-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX7-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX7-NEXT: s_waitcnt vmcnt(5)
+; GFX7-NEXT: v_cndmask_b32_e64 v30, v27, v28, s[4:5]
+; GFX7-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112
+; GFX7-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX7-NEXT: s_waitcnt vmcnt(3)
+; GFX7-NEXT: v_cndmask_b32_e64 v28, v23, v24, s[6:7]
+; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:236
+; GFX7-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX7-NEXT: s_waitcnt vmcnt(2)
+; GFX7-NEXT: v_cndmask_b32_e32 v29, v25, v26, vcc
+; GFX7-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:108
+; GFX7-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX7-NEXT: s_waitcnt vmcnt(2)
+; GFX7-NEXT: v_cndmask_b32_e64 v27, v22, v27, s[8:9]
+; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:104
+; GFX7-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX7-NEXT: s_waitcnt vmcnt(1)
+; GFX7-NEXT: v_cndmask_b32_e64 v26, v23, v25, s[10:11]
+; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:232
+; GFX7-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e64 v25, v23, v22, s[12:13]
+; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100
+; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:228
+; GFX7-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e64 v24, v23, v22, s[14:15]
+; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:224
+; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96
+; GFX7-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e64 v23, v22, v23, s[16:17]
+; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92
+; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:220
+; GFX7-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e64 v22, v31, v22, s[18:19]
+; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; GFX7-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v31, 1, v31
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v31
+; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:256
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v21
+; GFX7-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:216
+; GFX7-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v21, v32, v21, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v20
+; GFX7-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:212
+; GFX7-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v20, v32, v20, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
+; GFX7-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
+; GFX7-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v19, v19, v32, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
+; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:76
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:204
+; GFX7-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v32, v18, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
+; GFX7-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:200
+; GFX7-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v32, v17, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
+; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:196
+; GFX7-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v16, v32, v16, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
+; GFX7-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:192
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:64
+; GFX7-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v15, v15, v32, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v14
+; GFX7-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:60
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:188
+; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v14, v32, v14, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v13
+; GFX7-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:184
+; GFX7-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v13, v32, v13, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX7-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:180
+; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v12, v32, v12, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v11
+; GFX7-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48
+; GFX7-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v11, v11, v32, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX7-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:44
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:172
+; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v10, v32, v10, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX7-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:168
+; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v9, v32, v9, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX7-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:164
+; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v8, v32, v8, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX7-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
+; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v7, v7, v32, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX7-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:156
+; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v6, v32, v6, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX7-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:152
+; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v5, v32, v5, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148
+; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v32, v4, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX7-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:144
+; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v32, v3, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:140
+; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v32, v2, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX7-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:136
+; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v32, v1, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132
+; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v32, v0, vcc
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_vselect_v32bf16:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v22
+; GFX8-NEXT: v_and_b32_e32 v22, 1, v23
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v22
+; GFX8-NEXT: buffer_load_ushort v22, off, s[0:3], s32
+; GFX8-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX8-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v28
+; GFX8-NEXT: v_and_b32_e32 v28, 1, v29
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v24
+; GFX8-NEXT: v_and_b32_e32 v24, 1, v25
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v28
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v24
+; GFX8-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v26
+; GFX8-NEXT: v_and_b32_e32 v26, 1, v27
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v26
+; GFX8-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30
+; GFX8-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX8-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX8-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX8-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX8-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX8-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX8-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v22
+; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:60
+; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v22
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cndmask_b32_e64 v22, v23, v22, s[10:11]
+; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; GFX8-NEXT: v_cndmask_b32_e64 v23, v23, v24, s[12:13]
+; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:56
+; GFX8-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v24
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cndmask_b32_e64 v24, v25, v24, s[14:15]
+; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; GFX8-NEXT: v_cndmask_b32_e64 v25, v25, v26, s[16:17]
+; GFX8-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:52
+; GFX8-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:116
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v26
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cndmask_b32_e64 v26, v27, v26, s[18:19]
+; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; GFX8-NEXT: v_cndmask_b32_e64 v27, v27, v28, s[20:21]
+; GFX8-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:48
+; GFX8-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:112
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v28
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cndmask_b32_e64 v28, v29, v28, s[6:7]
+; GFX8-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; GFX8-NEXT: v_cndmask_b32_e64 v30, v29, v30, s[8:9]
+; GFX8-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:64
+; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v29
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cndmask_b32_e32 v29, v31, v29, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; GFX8-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[4:5]
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:108
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v21
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v32
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e32 v21, v34, v21, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v20
+; GFX8-NEXT: v_cndmask_b32_e32 v20, v33, v32, vcc
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:104
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v32
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e32 v19, v34, v19, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v18, v33, v32, vcc
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:36
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:100
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v32
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v34, v17, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v16, v33, v32, vcc
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:96
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v32
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v34, v15, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v14
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v33, v32, vcc
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:28
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:92
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v13
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v32
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v34, v13, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v33, v32, vcc
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:88
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v11
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v32
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v34, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v33, v32, vcc
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:20
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v32
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v34, v9, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v33, v32, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v7
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v32
+; GFX8-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v32, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
+; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v5
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v32, v34, v32, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX8-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8
+; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v34, v7, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; GFX8-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v34, v5, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v7
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v32
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v15
+; GFX8-NEXT: v_or_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v6, v12, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v7, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v17
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v31
+; GFX8-NEXT: v_or_b32_sdwa v8, v16, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v9, v18, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v11, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v12, v26, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v13, v24, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v14, v22, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v15, v29, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_vselect_v32bf16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v22
+; GFX9-NEXT: v_and_b32_e32 v22, 1, v23
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v22
+; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32
+; GFX9-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX9-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v28
+; GFX9-NEXT: v_and_b32_e32 v28, 1, v29
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v24
+; GFX9-NEXT: v_and_b32_e32 v24, 1, v25
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v28
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v24
+; GFX9-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v26
+; GFX9-NEXT: v_and_b32_e32 v26, 1, v27
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v26
+; GFX9-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30
+; GFX9-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX9-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX9-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX9-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX9-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX9-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX9-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX9-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX9-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX9-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX9-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX9-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX9-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX9-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v22
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:124
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v22
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e64 v22, v23, v22, s[10:11]
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; GFX9-NEXT: v_cndmask_b32_e64 v23, v23, v24, s[12:13]
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v24
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e64 v24, v25, v24, s[14:15]
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: v_cndmask_b32_e64 v25, v25, v26, s[16:17]
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:116
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v26
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e64 v26, v27, v26, s[18:19]
+; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; GFX9-NEXT: v_cndmask_b32_e64 v27, v27, v28, s[20:21]
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:112
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v28
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e64 v28, v29, v28, s[6:7]
+; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v29
+; GFX9-NEXT: v_cndmask_b32_e64 v30, v29, v30, s[8:9]
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v29
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e32 v29, v31, v29, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v31
+; GFX9-NEXT: v_cndmask_b32_e64 v31, v31, v32, s[4:5]
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:108
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v21
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX9-NEXT: v_cndmask_b32_e32 v21, v34, v21, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v20
+; GFX9-NEXT: v_cndmask_b32_e32 v20, v33, v32, vcc
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:104
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX9-NEXT: v_cndmask_b32_e32 v19, v34, v19, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
+; GFX9-NEXT: v_cndmask_b32_e32 v18, v33, v32, vcc
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:100
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX9-NEXT: v_cndmask_b32_e32 v17, v34, v17, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
+; GFX9-NEXT: v_cndmask_b32_e32 v16, v33, v32, vcc
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:96
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v32
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX9-NEXT: v_cndmask_b32_e32 v15, v34, v15, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v14
+; GFX9-NEXT: v_cndmask_b32_e32 v14, v33, v32, vcc
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:92
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v13
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v32
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v34, v13, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v33, v32, vcc
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:88
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v11
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v32
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v34, v11, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v33, v32, vcc
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v32
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v33
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v34, v9, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v33, v32, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v7
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v32
+; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v32, v7, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v5
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v32, v34, v32, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v34, v7, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v34, v5, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v7
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v32
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v33
+; GFX9-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v15
+; GFX9-NEXT: v_or_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v6, v12, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v7, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v31
+; GFX9-NEXT: v_or_b32_sdwa v8, v16, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v9, v18, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v11, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v12, v26, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v13, v24, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v14, v22, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v15, v29, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_vselect_v32bf16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
+; GFX10-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_mov_b32 exec_lo, s4
+; GFX10-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX10-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX10-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX10-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX10-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX10-NEXT: s_clause 0x15
+; GFX10-NEXT: buffer_load_ushort v36, off, s[0:3], s32
+; GFX10-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:64
+; GFX10-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:128
+; GFX10-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4
+; GFX10-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:68
+; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52
+; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:56
+; GFX10-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60
+; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:124
+; GFX10-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
+; GFX10-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:72
+; GFX10-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:12
+; GFX10-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:76
+; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:16
+; GFX10-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:80
+; GFX10-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20
+; GFX10-NEXT: buffer_load_dword v64, off, s[0:3], s32 offset:84
+; GFX10-NEXT: buffer_load_dword v65, off, s[0:3], s32 offset:24
+; GFX10-NEXT: buffer_load_dword v66, off, s[0:3], s32 offset:88
+; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:28
+; GFX10-NEXT: buffer_load_dword v68, off, s[0:3], s32 offset:92
+; GFX10-NEXT: buffer_load_dword v69, off, s[0:3], s32 offset:32
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v20
+; GFX10-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22
+; GFX10-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:36
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v24
+; GFX10-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:100
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v30
+; GFX10-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:40
+; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v0
+; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:104
+; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v2
+; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:44
+; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v4
+; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:108
+; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v6
+; GFX10-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:48
+; GFX10-NEXT: v_cmp_eq_u32_e64 s11, 1, v8
+; GFX10-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:120
+; GFX10-NEXT: v_cmp_eq_u32_e64 s12, 1, v10
+; GFX10-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:116
+; GFX10-NEXT: v_cmp_eq_u32_e64 s13, 1, v12
+; GFX10-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112
+; GFX10-NEXT: v_writelane_b32 v31, s30, 0
+; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX10-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX10-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX10-NEXT: v_writelane_b32 v31, s31, 1
+; GFX10-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX10-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX10-NEXT: v_writelane_b32 v31, s34, 2
+; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX10-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX10-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX10-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX10-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX10-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX10-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX10-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX10-NEXT: v_and_b32_e32 v23, 1, v23
+; GFX10-NEXT: v_and_b32_e32 v25, 1, v25
+; GFX10-NEXT: v_and_b32_e32 v27, 1, v27
+; GFX10-NEXT: v_and_b32_e32 v29, 1, v29
+; GFX10-NEXT: v_cmp_eq_u32_e64 s14, 1, v14
+; GFX10-NEXT: v_cmp_eq_u32_e64 s15, 1, v16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s16, 1, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s17, 1, v28
+; GFX10-NEXT: v_cmp_eq_u32_e64 s19, 1, v26
+; GFX10-NEXT: v_cmp_eq_u32_e64 s31, 1, v1
+; GFX10-NEXT: v_writelane_b32 v31, s35, 3
+; GFX10-NEXT: v_cmp_eq_u32_e64 s18, 1, v29
+; GFX10-NEXT: v_cmp_eq_u32_e64 s20, 1, v27
+; GFX10-NEXT: v_cmp_eq_u32_e64 s21, 1, v25
+; GFX10-NEXT: v_cmp_eq_u32_e64 s22, 1, v23
+; GFX10-NEXT: v_cmp_eq_u32_e64 s23, 1, v21
+; GFX10-NEXT: v_cmp_eq_u32_e64 s24, 1, v19
+; GFX10-NEXT: v_cmp_eq_u32_e64 s25, 1, v17
+; GFX10-NEXT: v_cmp_eq_u32_e64 s26, 1, v15
+; GFX10-NEXT: v_cmp_eq_u32_e64 s27, 1, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s28, 1, v11
+; GFX10-NEXT: v_cmp_eq_u32_e64 s29, 1, v7
+; GFX10-NEXT: v_cmp_eq_u32_e64 s30, 1, v3
+; GFX10-NEXT: v_cmp_eq_u32_e64 s34, 1, v5
+; GFX10-NEXT: v_cmp_eq_u32_e64 s35, 1, v9
+; GFX10-NEXT: s_waitcnt vmcnt(32)
+; GFX10-NEXT: v_and_b32_e32 v1, 1, v36
+; GFX10-NEXT: s_waitcnt vmcnt(31)
+; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v37
+; GFX10-NEXT: s_waitcnt vmcnt(30)
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v38
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v38, v37, s6
+; GFX10-NEXT: s_waitcnt vmcnt(29)
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v39
+; GFX10-NEXT: s_waitcnt vmcnt(28)
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v48, v39, s7
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v48
+; GFX10-NEXT: s_waitcnt vmcnt(23)
+; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v49
+; GFX10-NEXT: s_waitcnt vmcnt(22)
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v50, v49, s8
+; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v50
+; GFX10-NEXT: s_waitcnt vmcnt(21)
+; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v51
+; GFX10-NEXT: s_waitcnt vmcnt(20)
+; GFX10-NEXT: v_cndmask_b32_e64 v18, v52, v51, s9
+; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v52
+; GFX10-NEXT: s_waitcnt vmcnt(19)
+; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v53
+; GFX10-NEXT: s_waitcnt vmcnt(18)
+; GFX10-NEXT: v_cndmask_b32_e64 v23, v54, v53, s10
+; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v54
+; GFX10-NEXT: s_waitcnt vmcnt(17)
+; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v55
+; GFX10-NEXT: s_waitcnt vmcnt(16)
+; GFX10-NEXT: v_cndmask_b32_e64 v27, v64, v55, s11
+; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v64
+; GFX10-NEXT: s_waitcnt vmcnt(15)
+; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v65
+; GFX10-NEXT: s_waitcnt vmcnt(14)
+; GFX10-NEXT: v_cndmask_b32_e64 v36, v66, v65, s12
+; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v66
+; GFX10-NEXT: s_waitcnt vmcnt(13)
+; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v67
+; GFX10-NEXT: s_waitcnt vmcnt(12)
+; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v68
+; GFX10-NEXT: s_waitcnt vmcnt(11)
+; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v69
+; GFX10-NEXT: s_waitcnt vmcnt(10)
+; GFX10-NEXT: v_cndmask_b32_e64 v50, v20, v69, s14
+; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; GFX10-NEXT: s_waitcnt vmcnt(9)
+; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v22
+; GFX10-NEXT: s_waitcnt vmcnt(8)
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v24, v22, s15
+; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; GFX10-NEXT: s_waitcnt vmcnt(7)
+; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v30
+; GFX10-NEXT: s_waitcnt vmcnt(6)
+; GFX10-NEXT: v_cndmask_b32_e64 v30, v0, v30, s16
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: s_waitcnt vmcnt(5)
+; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v34
+; GFX10-NEXT: v_cndmask_b32_e64 v34, v35, v34, s17
+; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v35
+; GFX10-NEXT: s_waitcnt vmcnt(4)
+; GFX10-NEXT: v_cndmask_b32_e64 v55, v4, v2, s5
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v4
+; GFX10-NEXT: s_waitcnt vmcnt(3)
+; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v6
+; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v32
+; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v33
+; GFX10-NEXT: s_waitcnt vmcnt(2)
+; GFX10-NEXT: v_cndmask_b32_e64 v33, v8, v33, s19
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: v_cndmask_b32_e64 v32, v10, v32, s4
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_cndmask_b32_e32 v66, v12, v6, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v12
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v35, v54, s18
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v65, s20
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v64, s21
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v6, v4, s22
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v53, s23
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v52, s24
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v24, v51, s25
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v20, v49, s26
+; GFX10-NEXT: v_cndmask_b32_e64 v20, v48, v38, s27
+; GFX10-NEXT: v_cndmask_b32_e64 v24, v37, v29, s28
+; GFX10-NEXT: v_cndmask_b32_e64 v21, v25, v21, s29
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v7, s31
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v16, v13, s30
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v19, v17, s34
+; GFX10-NEXT: v_cndmask_b32_e64 v16, v28, v26, s35
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v39, v68, v67, s13
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v24
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v20
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v3
+; GFX10-NEXT: v_or_b32_sdwa v0, v9, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v18, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v23, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v4, v27, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v5, v36, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v6, v39, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v7, v50, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v8, v22, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v9, v30, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v10, v55, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v11, v66, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v12, v32, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v13, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v14, v34, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v15, v15, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_readlane_b32 s35, v31, 3
+; GFX10-NEXT: v_readlane_b32 s34, v31, 2
+; GFX10-NEXT: v_readlane_b32 s31, v31, 1
+; GFX10-NEXT: v_readlane_b32 s30, v31, 0
+; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
+; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_mov_b32 exec_lo, s4
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v32bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_clause 0x20
+; GFX11-NEXT: scratch_load_b32 v31, off, s32 offset:4
+; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:68
+; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8
+; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:72
+; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:12
+; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:76
+; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:16
+; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:80
+; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:20
+; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:84
+; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:24
+; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:88
+; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:28
+; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:92
+; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:32
+; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:96
+; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:36
+; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:100
+; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:40
+; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:104
+; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:44
+; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:108
+; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:48
+; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:112
+; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:52
+; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:116
+; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:56
+; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:120
+; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:60
+; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:124
+; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:64
+; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:128
+; GFX11-NEXT: scratch_load_u16 v87, off, s32
+; GFX11-NEXT: s_waitcnt vmcnt(32)
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v31
+; GFX11-NEXT: s_waitcnt vmcnt(31)
+; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v32
+; GFX11-NEXT: s_waitcnt vmcnt(30)
+; GFX11-NEXT: v_lshrrev_b32_e32 v98, 16, v33
+; GFX11-NEXT: s_waitcnt vmcnt(29)
+; GFX11-NEXT: v_lshrrev_b32_e32 v99, 16, v34
+; GFX11-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX11-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX11-NEXT: s_waitcnt vmcnt(28)
+; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v35
+; GFX11-NEXT: s_waitcnt vmcnt(27)
+; GFX11-NEXT: v_lshrrev_b32_e32 v101, 16, v36
+; GFX11-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: s_waitcnt vmcnt(26)
+; GFX11-NEXT: v_lshrrev_b32_e32 v102, 16, v37
+; GFX11-NEXT: s_waitcnt vmcnt(25)
+; GFX11-NEXT: v_lshrrev_b32_e32 v103, 16, v38
+; GFX11-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX11-NEXT: s_waitcnt vmcnt(24)
+; GFX11-NEXT: v_lshrrev_b32_e32 v112, 16, v39
+; GFX11-NEXT: s_waitcnt vmcnt(23)
+; GFX11-NEXT: v_lshrrev_b32_e32 v113, 16, v48
+; GFX11-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX11-NEXT: s_waitcnt vmcnt(22)
+; GFX11-NEXT: v_lshrrev_b32_e32 v114, 16, v49
+; GFX11-NEXT: s_waitcnt vmcnt(21)
+; GFX11-NEXT: v_lshrrev_b32_e32 v115, 16, v50
+; GFX11-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX11-NEXT: s_waitcnt vmcnt(20)
+; GFX11-NEXT: v_lshrrev_b32_e32 v116, 16, v51
+; GFX11-NEXT: s_waitcnt vmcnt(19)
+; GFX11-NEXT: v_lshrrev_b32_e32 v117, 16, v52
+; GFX11-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX11-NEXT: s_waitcnt vmcnt(18)
+; GFX11-NEXT: v_lshrrev_b32_e32 v118, 16, v53
+; GFX11-NEXT: s_waitcnt vmcnt(17)
+; GFX11-NEXT: v_lshrrev_b32_e32 v119, 16, v54
+; GFX11-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX11-NEXT: s_waitcnt vmcnt(16)
+; GFX11-NEXT: v_lshrrev_b32_e32 v128, 16, v55
+; GFX11-NEXT: s_waitcnt vmcnt(15)
+; GFX11-NEXT: v_lshrrev_b32_e32 v129, 16, v64
+; GFX11-NEXT: s_waitcnt vmcnt(4)
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 16, v83
+; GFX11-NEXT: s_waitcnt vmcnt(3)
+; GFX11-NEXT: v_cndmask_b32_e32 v83, v84, v83, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v30
+; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: s_waitcnt vmcnt(2)
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v85
+; GFX11-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v130, 16, v65
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_cndmask_b32_e32 v85, v86, v85, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26
+; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v131, 16, v66
+; GFX11-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v132, 16, v67
+; GFX11-NEXT: v_cndmask_b32_e32 v26, v82, v81, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24
+; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v68
+; GFX11-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v134, 16, v69
+; GFX11-NEXT: v_cndmask_b32_e32 v24, v80, v71, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22
+; GFX11-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v135, 16, v70
+; GFX11-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v144, 16, v71
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v70, v69, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20
+; GFX11-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v145, 16, v80
+; GFX11-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v146, 16, v81
+; GFX11-NEXT: v_cndmask_b32_e32 v20, v68, v67, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
+; GFX11-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v147, 16, v82
+; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v84
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v66, v65, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX11-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_and_b32_e32 v87, 1, v87
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v86
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v64, v55, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
+; GFX11-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff, v20
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v54, v53, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX11-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX11-NEXT: v_and_b32_e32 v24, 0xffff, v24
+; GFX11-NEXT: v_and_b32_e32 v26, 0xffff, v26
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v52, v51, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX11-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v50, v49, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
+; GFX11-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v48, v39, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: v_and_b32_e32 v23, 1, v23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v38, v37, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v36, v35, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_and_b32_e32 v27, 1, v27
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v34, v33, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_and_b32_e32 v25, 1, v25
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v32, v31, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v87
+; GFX11-NEXT: v_and_b32_e32 v29, 1, v29
+; GFX11-NEXT: v_and_b32_e32 v31, 0xffff, v85
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v30, v86, v30, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29
+; GFX11-NEXT: v_and_b32_e32 v29, 0xffff, v83
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-NEXT: v_cndmask_b32_e32 v28, v84, v28, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27
+; GFX11-NEXT: v_dual_cndmask_b32 v27, v147, v146 :: v_dual_lshlrev_b32 v28, 16, v28
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v145, v144, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-NEXT: v_cndmask_b32_e32 v23, v135, v134, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v133, v132, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v131, v130, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v129, v128, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v119, v118, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v117, v116, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v115, v114, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v113, v112, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v103, v102, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v101, v100, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v99, v98, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v97, v96, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
+; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
+; GFX11-NEXT: v_or_b32_e32 v6, v12, v13
+; GFX11-NEXT: v_or_b32_e32 v7, v14, v15
+; GFX11-NEXT: v_or_b32_e32 v8, v16, v17
+; GFX11-NEXT: v_or_b32_e32 v9, v18, v19
+; GFX11-NEXT: v_or_b32_e32 v10, v20, v21
+; GFX11-NEXT: v_or_b32_e32 v11, v22, v23
+; GFX11-NEXT: v_or_b32_e32 v12, v24, v25
+; GFX11-NEXT: v_or_b32_e32 v13, v26, v27
+; GFX11-NEXT: v_or_b32_e32 v14, v29, v28
+; GFX11-NEXT: v_or_b32_e32 v15, v31, v30
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %op = select <32 x i1> %cond, <32 x bfloat> %a, <32 x bfloat> %b
+ ret <32 x bfloat> %op
+}
+
declare bfloat @llvm.fma.bf16(bfloat, bfloat, bfloat)
declare <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat>, <2 x bfloat>, <2 x bfloat>)
declare <3 x bfloat> @llvm.fma.v3bf16(<3 x bfloat>, <3 x bfloat>, <3 x bfloat>)
>From f88f11542792d09e9ac48ed2075f7f5fc67ad38a Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 27 Dec 2023 11:38:38 +0700
Subject: [PATCH 7/7] AMDGPU: Don't assert on select of v32i16/v32f16
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/select-vectors.ll | 46 +
llvm/test/CodeGen/AMDGPU/select.f16.ll | 1815 ++++++++++++++++++++
3 files changed, 1862 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index fc119aa61d01a2..f3547db9e9bd94 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5304,7 +5304,7 @@ SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v8i16 ||
VT == MVT::v8f16 || VT == MVT::v4f32 || VT == MVT::v16i16 ||
VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 ||
- VT == MVT::v32f32);
+ VT == MVT::v32f32 || VT == MVT::v32f16 || VT == MVT::v32i16);
SDValue Lo0, Hi0;
SDValue Op0 = Op.getOperand(0);
diff --git a/llvm/test/CodeGen/AMDGPU/select-vectors.ll b/llvm/test/CodeGen/AMDGPU/select-vectors.ll
index b1cdc79016fc93..30ace39464682b 100644
--- a/llvm/test/CodeGen/AMDGPU/select-vectors.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-vectors.ll
@@ -152,6 +152,52 @@ define amdgpu_kernel void @v_select_v8i16(ptr addrspace(1) %out, ptr addrspace(1
ret void
}
+; GCN-LABEL: {{^}}v_select_v16i16:
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN-NOT: cndmask
+define amdgpu_kernel void @v_select_v16i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, i32 %c) #0 {
+ %a = load <16 x i16>, ptr addrspace(1) %a.ptr
+ %b = load <16 x i16>, ptr addrspace(1) %b.ptr
+ %cmp = icmp eq i32 %c, 0
+ %select = select i1 %cmp, <16 x i16> %a, <16 x i16> %b
+ store <16 x i16> %select, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_select_v32i16:
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN: v_cndmask_b32_e32
+; GCN-NOT: cndmask
+define amdgpu_kernel void @v_select_v32i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr, i32 %c) #0 {
+ %a = load <32 x i16>, ptr addrspace(1) %a.ptr
+ %b = load <32 x i16>, ptr addrspace(1) %b.ptr
+ %cmp = icmp eq i32 %c, 0
+ %select = select i1 %cmp, <32 x i16> %a, <32 x i16> %b
+ store <32 x i16> %select, ptr addrspace(1) %out, align 4
+ ret void
+}
+
; FIXME: Expansion with bitwise operations may be better if doing a
; vector select with SGPR inputs.
diff --git a/llvm/test/CodeGen/AMDGPU/select.f16.ll b/llvm/test/CodeGen/AMDGPU/select.f16.ll
index adce63c7e45e7f..db0d9c1aaa216a 100644
--- a/llvm/test/CodeGen/AMDGPU/select.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select.f16.ll
@@ -119,6 +119,7 @@ define amdgpu_kernel void @select_f16(
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
+
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b,
@@ -1317,3 +1318,1817 @@ entry:
store <2 x half> %r.val, ptr addrspace(1) %r
ret void
}
+
+define <4 x half> @v_select_v4f16(<4 x half> %a, <4 x half> %b, i32 %cond) {
+; SI-LABEL: v_select_v4f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_select_v4f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v4f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %cond, 0
+ %select = select i1 %cmp, <4 x half> %a, <4 x half> %b
+ ret <4 x half> %select
+}
+
+define <4 x half> @v_vselect_v4f16(<4 x half> %a, <4 x half> %b, <4 x i32> %cond) {
+; SI-LABEL: v_vselect_v4f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; SI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; SI-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
+; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11
+; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_vselect_v4f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; VI-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; VI-NEXT: v_cndmask_b32_e32 v5, v9, v8, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v4f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v11, v10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX11-NEXT: v_perm_b32 v1, v7, v1, 0x5040100
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq <4 x i32> %cond, zeroinitializer
+ %select = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
+ ret <4 x half> %select
+}
+
+define <8 x half> @v_select_v8f16(<8 x half> %a, <8 x half> %b, i32 %cond) {
+; SI-LABEL: v_select_v8f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v15
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v13
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; SI-NEXT: v_or_b32_e32 v7, v14, v7
+; SI-NEXT: v_or_b32_e32 v5, v12, v5
+; SI-NEXT: v_or_b32_e32 v3, v10, v3
+; SI-NEXT: v_or_b32_e32 v1, v8, v1
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
+; SI-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v7
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_select_v8f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v8f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %cond, 0
+ %select = select i1 %cmp, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %select
+}
+
+define <8 x half> @v_vselect_v8f16(<8 x half> %a, <8 x half> %b, <8 x i32> %cond) {
+; SI-LABEL: v_vselect_v8f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; SI-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
+; SI-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v19
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v20
+; SI-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v21
+; SI-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v22
+; SI-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v23
+; SI-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_vselect_v8f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v7
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15
+; VI-NEXT: v_cndmask_b32_e32 v15, v17, v16, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v6
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v13
+; VI-NEXT: v_cndmask_b32_e32 v13, v17, v16, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11
+; VI-NEXT: v_cndmask_b32_e32 v11, v17, v16, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v0
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v4
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; VI-NEXT: v_cndmask_b32_e32 v9, v17, v16, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14
+; VI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
+; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
+; VI-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
+; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v13
+; VI-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v15
+; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v8f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v17, v16, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v6
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v17, v16, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v19, v18, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v21, v20, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v2, v13, v2, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v10
+; GFX11-NEXT: v_perm_b32 v0, v9, v0, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, v11, v1, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX11-NEXT: v_perm_b32 v3, v15, v3, 0x5040100
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq <8 x i32> %cond, zeroinitializer
+ %select = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %select
+}
+
+define <16 x half> @v_select_v16f16(<16 x half> %a, <16 x half> %b, i32 %cond) {
+; SI-LABEL: v_select_v16f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v29
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v28
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v27
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v26
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_or_b32_e32 v11, v15, v11
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:4
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
+; SI-NEXT: v_cvt_f16_f32_e32 v26, v30
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
+; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
+; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v17
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_or_b32_e32 v9, v24, v25
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_or_b32_e32 v5, v20, v21
+; SI-NEXT: v_or_b32_e32 v3, v18, v3
+; SI-NEXT: v_or_b32_e32 v1, v16, v1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v28
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v26, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
+; SI-NEXT: v_cndmask_b32_e32 v15, v22, v6, vcc
+; SI-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc
+; SI-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc
+; SI-NEXT: v_cndmask_b32_e32 v13, v13, v12, vcc
+; SI-NEXT: v_cndmask_b32_e32 v16, v7, v14, vcc
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v13
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_select_v16f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; VI-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; VI-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; VI-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; VI-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
+; VI-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v16f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v12, v4 :: v_dual_cndmask_b32 v5, v13, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %cond, 0
+ %select = select i1 %cmp, <16 x half> %a, <16 x half> %b
+ ret <16 x half> %select
+}
+
+define <16 x half> @v_vselect_v16f16(<16 x half> %a, <16 x half> %b, <16 x i32> %cond) {
+; SI-LABEL: v_vselect_v16f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:8
+; SI-NEXT: v_cndmask_b32_e64 v0, v16, v0, s[6:7]
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v17
+; SI-NEXT: v_cvt_f16_f32_e32 v17, v27
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v17, v17
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
+; SI-NEXT: v_cndmask_b32_e64 v1, v16, v1, s[8:9]
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v18
+; SI-NEXT: v_cvt_f16_f32_e32 v18, v28
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:16
+; SI-NEXT: v_cndmask_b32_e64 v2, v16, v2, s[10:11]
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v19
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v29
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
+; SI-NEXT: v_cndmask_b32_e64 v3, v16, v3, s[12:13]
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v20
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v30
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v20, v20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[14:15], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:32
+; SI-NEXT: v_cndmask_b32_e64 v4, v16, v4, s[14:15]
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v21
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cndmask_b32_e64 v5, v16, v5, s[4:5]
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v22
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cndmask_b32_e32 v6, v16, v6, vcc
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v23
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v31
+; SI-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[16:17]
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v24
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v25
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v26
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cndmask_b32_e32 v10, v16, v10, vcc
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:52
+; SI-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; SI-NEXT: v_cndmask_b32_e32 v12, v18, v12, vcc
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:64
+; SI-NEXT: v_cndmask_b32_e32 v13, v19, v13, vcc
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
+; SI-NEXT: v_cndmask_b32_e32 v14, v20, v14, vcc
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_vselect_v16f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: v_writelane_b32 v31, s30, 0
+; VI-NEXT: v_writelane_b32 v31, s31, 1
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; VI-NEXT: v_cmp_eq_u32_e64 s[18:19], 0, v17
+; VI-NEXT: v_cmp_eq_u32_e64 s[30:31], 0, v29
+; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v14
+; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18
+; VI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v24
+; VI-NEXT: v_cmp_eq_u32_e64 s[28:29], 0, v27
+; VI-NEXT: v_cndmask_b32_e64 v16, v17, v16, s[30:31]
+; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
+; VI-NEXT: v_cmp_eq_u32_e64 s[20:21], 0, v19
+; VI-NEXT: v_cndmask_b32_e64 v17, v18, v17, s[28:29]
+; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v12
+; VI-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[10:11]
+; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32
+; VI-NEXT: v_cmp_eq_u32_e64 s[26:27], 0, v25
+; VI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v20
+; VI-NEXT: v_cmp_eq_u32_e64 s[24:25], 0, v23
+; VI-NEXT: v_cndmask_b32_e64 v18, v19, v18, s[26:27]
+; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; VI-NEXT: v_cmp_eq_u32_e64 s[22:23], 0, v21
+; VI-NEXT: v_cndmask_b32_e64 v19, v20, v19, s[24:25]
+; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v10
+; VI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v22
+; VI-NEXT: v_cndmask_b32_e64 v20, v21, v20, s[22:23]
+; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v9
+; VI-NEXT: v_cndmask_b32_e64 v21, v22, v21, s[20:21]
+; VI-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[4:5]
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v21
+; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v0
+; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v8
+; VI-NEXT: v_cndmask_b32_e64 v2, v10, v2, s[6:7]
+; VI-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v20
+; VI-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v26
+; VI-NEXT: v_cndmask_b32_e64 v22, v23, v22, s[18:19]
+; VI-NEXT: v_cndmask_b32_e64 v3, v11, v3, s[8:9]
+; VI-NEXT: v_or_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v19
+; VI-NEXT: v_cndmask_b32_e64 v5, v13, v5, s[12:13]
+; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v15
+; VI-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
+; VI-NEXT: v_or_b32_sdwa v3, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v18
+; VI-NEXT: v_cmp_eq_u32_e64 s[14:15], 0, v28
+; VI-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v30
+; VI-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v4, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v17
+; VI-NEXT: v_cndmask_b32_e64 v6, v14, v6, s[14:15]
+; VI-NEXT: v_cndmask_b32_e64 v7, v15, v7, s[16:17]
+; VI-NEXT: v_or_b32_sdwa v5, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v16
+; VI-NEXT: v_or_b32_sdwa v6, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_readlane_b32 s31, v31, 1
+; VI-NEXT: v_readlane_b32 s30, v31, 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
+; VI-NEXT: v_cndmask_b32_e32 v8, v13, v11, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v16f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v14
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v22
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v20
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v29
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v35, v34, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v27
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v37, v36, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v6, v8, v6, 0x5040100
+; GFX11-NEXT: v_perm_b32 v5, v9, v5, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v39, v38, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v53, v52, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v4, v10, v4, 0x5040100
+; GFX11-NEXT: v_perm_b32 v1, v11, v1, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v55, v54, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v21
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v51, v50, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v23
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v49, v48, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v2, v13, v2, 0x5040100
+; GFX11-NEXT: v_perm_b32 v3, v14, v3, 0x5040100
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v31
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v33, v32, vcc_lo
+; GFX11-NEXT: v_perm_b32 v0, v12, v0, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v7, v11, v7, 0x5040100
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq <16 x i32> %cond, zeroinitializer
+ %select = select <16 x i1> %cmp, <16 x half> %a, <16 x half> %b
+ ret <16 x half> %select
+}
+
+define <32 x half> @v_select_v32f16(<32 x half> %a, <32 x half> %b, i32 %cond) {
+; SI-LABEL: v_select_v32f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v20, v20, v21
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56
+; SI-NEXT: v_or_b32_e32 v10, v10, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:48
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:40
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:32
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:16
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
+; SI-NEXT: v_or_b32_e32 v22, v22, v23
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v30
+; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
+; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
+; SI-NEXT: v_or_b32_e32 v24, v24, v25
+; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_or_b32_e32 v26, v26, v27
+; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
+; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
+; SI-NEXT: v_or_b32_e32 v28, v28, v29
+; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_or_b32_e32 v18, v18, v19
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_or_b32_e32 v16, v16, v17
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:124
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
+; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
+; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; SI-NEXT: v_or_b32_e32 v29, v30, v29
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_or_b32_e32 v30, v31, v30
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_or_b32_e32 v31, v32, v31
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:76
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
+; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v19, v32, v19
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:68
+; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v17, v32, v17
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v15, v32, v15
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v13, v32, v13
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v11, v32, v11
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v9, v32, v9
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v7, v32, v7
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v5, v32, v5
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v3, v32, v3
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_or_b32_e32 v1, v32, v1
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:132
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v32
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc
+; SI-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc
+; SI-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc
+; SI-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc
+; SI-NEXT: v_cndmask_b32_e32 v13, v13, v12, vcc
+; SI-NEXT: v_cndmask_b32_e32 v15, v15, v14, vcc
+; SI-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc
+; SI-NEXT: v_cndmask_b32_e32 v19, v19, v18, vcc
+; SI-NEXT: v_cndmask_b32_e32 v31, v31, v20, vcc
+; SI-NEXT: v_cndmask_b32_e32 v30, v30, v22, vcc
+; SI-NEXT: v_cndmask_b32_e32 v29, v29, v24, vcc
+; SI-NEXT: v_cndmask_b32_e32 v27, v27, v26, vcc
+; SI-NEXT: v_cndmask_b32_e32 v32, v25, v28, vcc
+; SI-NEXT: v_cndmask_b32_e32 v33, v23, v21, vcc
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v9
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v11
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v13
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v15
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_cvt_f32_f16_e32 v18, v19
+; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; SI-NEXT: v_cvt_f32_f16_e32 v20, v31
+; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v30
+; SI-NEXT: v_cvt_f32_f16_e32 v24, v29
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v29
+; SI-NEXT: v_cvt_f32_f16_e32 v26, v27
+; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v32
+; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v17, v17
+; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
+; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
+; SI-NEXT: v_cvt_f32_f16_e32 v22, v30
+; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
+; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
+; SI-NEXT: v_cvt_f32_f16_e32 v27, v27
+; SI-NEXT: v_cvt_f32_f16_e32 v28, v32
+; SI-NEXT: v_cvt_f32_f16_e32 v29, v29
+; SI-NEXT: v_cvt_f32_f16_e32 v30, v33
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_select_v32f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; VI-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
+; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32
+; VI-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; VI-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; VI-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; VI-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; VI-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; VI-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; VI-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; VI-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; VI-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; VI-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; VI-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; VI-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_select_v32f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: scratch_load_b32 v31, off, s32 offset:4
+; GFX11-NEXT: scratch_load_b32 v32, off, s32
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v31
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v20, v4 :: v_dual_cndmask_b32 v5, v21, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
+; GFX11-NEXT: v_dual_cndmask_b32 v8, v24, v8 :: v_dual_cndmask_b32 v9, v25, v9
+; GFX11-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
+; GFX11-NEXT: v_dual_cndmask_b32 v12, v28, v12 :: v_dual_cndmask_b32 v13, v29, v13
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_dual_cndmask_b32 v14, v30, v14 :: v_dual_cndmask_b32 v15, v32, v15
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq i32 %cond, 0
+ %select = select i1 %cmp, <32 x half> %a, <32 x half> %b
+ ret <32 x half> %select
+}
+
+define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32> %cond) {
+; SI-LABEL: v_vselect_v32f16:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
+; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
+; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
+; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
+; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
+; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
+; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
+; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
+; SI-NEXT: v_cvt_f32_f16_e32 v17, v17
+; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
+; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
+; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
+; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
+; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
+; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
+; SI-NEXT: v_cvt_f32_f16_e32 v20, v20
+; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
+; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
+; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
+; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
+; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
+; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
+; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
+; SI-NEXT: v_cvt_f32_f16_e32 v24, v24
+; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
+; SI-NEXT: v_cvt_f32_f16_e32 v26, v26
+; SI-NEXT: v_cvt_f32_f16_e32 v27, v27
+; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
+; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
+; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128
+; SI-NEXT: v_cvt_f32_f16_e32 v28, v28
+; SI-NEXT: v_cvt_f32_f16_e32 v29, v29
+; SI-NEXT: v_cvt_f32_f16_e32 v30, v30
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:136
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
+; SI-NEXT: v_cvt_f32_f16_e32 v32, v32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[14:15], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:140
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[10:11], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:156
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:160
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e64 v0, v31, v0, s[16:17]
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:8
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e64 v1, v31, v1, s[14:15]
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e64 v2, v31, v2, s[12:13]
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e64 v3, v31, v3, s[10:11]
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e64 v4, v31, v4, s[8:9]
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e64 v5, v31, v5, s[6:7]
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e64 v6, v31, v6, s[4:5]
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v7, v31, v7, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:164
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v8, v31, v8, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:168
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v9, v31, v9, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v10, v31, v10, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:176
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v11, v31, v11, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:180
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v12, v31, v12, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:56
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v13, v31, v13, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:188
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v14, v31, v14, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:192
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:64
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v15, v31, v15, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:196
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v16, v31, v16, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:200
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v17, v31, v17, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:204
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v18, v31, v18, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:208
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v19, v31, v19, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:212
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v20, v31, v20, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:216
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:88
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v21, v31, v21, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:220
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v22, v31, v22, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:224
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v23, v31, v23, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v24, v31, v24, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:232
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:104
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v25, v31, v25, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:236
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v26, v31, v26, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:240
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v27, v31, v27, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:244
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v28, v31, v28, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:248
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:120
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v29, v31, v29, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:252
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:124
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v30, v31, v30, vcc
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:256
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
+; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
+; SI-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_vselect_v32f16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:120
+; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:112
+; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:104
+; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:96
+; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88
+; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80
+; VI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:72
+; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32
+; VI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:128
+; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:64
+; VI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56
+; VI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
+; VI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40
+; VI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:32
+; VI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:24
+; VI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:124
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:116
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v14
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v30
+; VI-NEXT: v_lshrrev_b32_e32 v44, 16, v13
+; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v29
+; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v12
+; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v28
+; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v11
+; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v27
+; VI-NEXT: v_lshrrev_b32_e32 v58, 16, v10
+; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v26
+; VI-NEXT: v_lshrrev_b32_e32 v60, 16, v9
+; VI-NEXT: s_waitcnt vmcnt(14)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v36
+; VI-NEXT: v_cndmask_b32_e32 v36, v43, v38, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v35
+; VI-NEXT: v_cndmask_b32_e32 v35, v45, v44, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v34
+; VI-NEXT: v_cndmask_b32_e32 v34, v47, v46, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v33
+; VI-NEXT: v_cndmask_b32_e32 v33, v57, v56, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v32
+; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v25
+; VI-NEXT: v_cndmask_b32_e32 v32, v59, v58, vcc
+; VI-NEXT: s_waitcnt vmcnt(13)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v8
+; VI-NEXT: v_lshrrev_b32_e32 v44, 16, v24
+; VI-NEXT: v_cndmask_b32_e32 v38, v38, v60, vcc
+; VI-NEXT: s_waitcnt vmcnt(12)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v39
+; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v15
+; VI-NEXT: v_cndmask_b32_e32 v39, v44, v43, vcc
+; VI-NEXT: s_waitcnt vmcnt(11)
+; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v37
+; VI-NEXT: s_waitcnt vmcnt(10)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v55
+; VI-NEXT: v_cndmask_b32_e32 v31, v31, v45, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v7
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v23
+; VI-NEXT: s_waitcnt vmcnt(9)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v50
+; VI-NEXT: v_cndmask_b32_e32 v50, v43, v55, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v6
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v22
+; VI-NEXT: s_waitcnt vmcnt(8)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v53
+; VI-NEXT: v_cndmask_b32_e32 v53, v43, v55, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v5
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v21
+; VI-NEXT: s_waitcnt vmcnt(7)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v54
+; VI-NEXT: v_cndmask_b32_e32 v54, v43, v55, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v4
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v20
+; VI-NEXT: s_waitcnt vmcnt(6)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v52
+; VI-NEXT: v_cndmask_b32_e32 v52, v43, v55, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v3
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v19
+; VI-NEXT: s_waitcnt vmcnt(5)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v51
+; VI-NEXT: v_cndmask_b32_e32 v51, v43, v55, vcc
+; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v18
+; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:108
+; VI-NEXT: s_waitcnt vmcnt(5)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v49
+; VI-NEXT: v_cndmask_b32_e32 v49, v43, v55, vcc
+; VI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:100
+; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:92
+; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v1
+; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
+; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:84
+; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:76
+; VI-NEXT: s_waitcnt vmcnt(8)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v48
+; VI-NEXT: v_cndmask_b32_e32 v48, v46, v43, vcc
+; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:68
+; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:60
+; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:52
+; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v0
+; VI-NEXT: v_lshrrev_b32_e32 v58, 16, v16
+; VI-NEXT: s_waitcnt vmcnt(10)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v40
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:44
+; VI-NEXT: v_cndmask_b32_e32 v46, v58, v46, vcc
+; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:36
+; VI-NEXT: s_waitcnt vmcnt(11)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v41
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:28
+; VI-NEXT: v_cndmask_b32_e32 v15, v37, v15, vcc
+; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
+; VI-NEXT: s_waitcnt vmcnt(12)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v42
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:12
+; VI-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc
+; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:4
+; VI-NEXT: s_waitcnt vmcnt(13)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v44
+; VI-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; VI-NEXT: s_waitcnt vmcnt(12)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v55
+; VI-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; VI-NEXT: s_waitcnt vmcnt(11)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v45
+; VI-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; VI-NEXT: s_waitcnt vmcnt(10)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v47
+; VI-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; VI-NEXT: s_waitcnt vmcnt(9)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v56
+; VI-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; VI-NEXT: s_waitcnt vmcnt(8)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v43
+; VI-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; VI-NEXT: s_waitcnt vmcnt(7)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v57
+; VI-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; VI-NEXT: s_waitcnt vmcnt(6)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v59
+; VI-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; VI-NEXT: s_waitcnt vmcnt(5)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v40
+; VI-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; VI-NEXT: s_waitcnt vmcnt(4)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v58
+; VI-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v41
+; VI-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v37
+; VI-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v42
+; VI-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v30
+; VI-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v46
+; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; VI-NEXT: v_or_b32_sdwa v0, v0, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v48
+; VI-NEXT: v_or_b32_sdwa v1, v1, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v49
+; VI-NEXT: v_or_b32_sdwa v2, v2, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v51
+; VI-NEXT: v_or_b32_sdwa v3, v3, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
+; VI-NEXT: v_or_b32_sdwa v4, v4, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v54
+; VI-NEXT: v_or_b32_sdwa v5, v5, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v53
+; VI-NEXT: v_or_b32_sdwa v6, v6, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
+; VI-NEXT: v_or_b32_sdwa v7, v7, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v39
+; VI-NEXT: v_or_b32_sdwa v8, v8, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v38
+; VI-NEXT: v_or_b32_sdwa v9, v9, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
+; VI-NEXT: v_or_b32_sdwa v10, v10, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
+; VI-NEXT: v_or_b32_sdwa v11, v11, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v34
+; VI-NEXT: v_or_b32_sdwa v12, v12, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v35
+; VI-NEXT: v_or_b32_sdwa v13, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v36
+; VI-NEXT: v_or_b32_sdwa v14, v14, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v31
+; VI-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_vselect_v32f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_clause 0x20
+; GFX11-NEXT: scratch_load_b32 v31, off, s32 offset:120
+; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:112
+; GFX11-NEXT: scratch_load_b32 v33, off, s32
+; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:104
+; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:96
+; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:88
+; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:80
+; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:72
+; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:64
+; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:56
+; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:48
+; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:40
+; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:32
+; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:24
+; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:16
+; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:8
+; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:124
+; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:116
+; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:108
+; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:100
+; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:92
+; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:84
+; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:76
+; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:68
+; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:60
+; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:52
+; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:44
+; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:36
+; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:28
+; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:12
+; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:4
+; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:20
+; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:128
+; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v98, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v99, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v101, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v102, 16, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v103, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v112, 16, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v113, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v114, 16, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v115, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v116, 16, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v117, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v118, 16, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v119, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v128, 16, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v129, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v130, 16, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v131, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v132, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v134, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v135, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v144, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v145, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v146, 16, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v147, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v15
+; GFX11-NEXT: s_waitcnt vmcnt(32)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v31
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v17
+; GFX11-NEXT: v_cndmask_b32_e32 v97, v98, v97, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(31)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v98, 16, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v99, v100, v99, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(29)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v34
+; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v33
+; GFX11-NEXT: v_cndmask_b32_e32 v34, v102, v101, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(28)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v35
+; GFX11-NEXT: v_cndmask_b32_e32 v35, v112, v103, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(27)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v36
+; GFX11-NEXT: v_cndmask_b32_e32 v36, v114, v113, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(26)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v37
+; GFX11-NEXT: v_cndmask_b32_e32 v37, v116, v115, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(25)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v38
+; GFX11-NEXT: v_cndmask_b32_e32 v38, v118, v117, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(24)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v39
+; GFX11-NEXT: v_cndmask_b32_e32 v39, v128, v119, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(23)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v48
+; GFX11-NEXT: v_cndmask_b32_e32 v48, v130, v129, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(22)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v49
+; GFX11-NEXT: v_cndmask_b32_e32 v49, v132, v131, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(21)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v50
+; GFX11-NEXT: v_cndmask_b32_e32 v50, v134, v133, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(20)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v51
+; GFX11-NEXT: v_cndmask_b32_e32 v51, v144, v135, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(19)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v52
+; GFX11-NEXT: v_cndmask_b32_e32 v52, v146, v145, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(18)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v53
+; GFX11-NEXT: v_cndmask_b32_e32 v31, v31, v147, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(17)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v54
+; GFX11-NEXT: v_cndmask_b32_e32 v32, v32, v98, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(16)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v55
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v33, v15, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(15)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v64
+; GFX11-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(14)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v65
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v14, v97, v14, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(13)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v66
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(12)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v67
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v12, v34, v12, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(11)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v68
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(10)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v69
+; GFX11-NEXT: v_perm_b32 v13, v99, v13, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v10, v36, v10, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(9)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v70
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(8)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v71
+; GFX11-NEXT: v_perm_b32 v11, v35, v11, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v8, v38, v8, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(7)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v80
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(6)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v81
+; GFX11-NEXT: v_perm_b32 v9, v37, v9, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v6, v48, v6, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(5)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v82
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(4)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v83
+; GFX11-NEXT: v_perm_b32 v7, v39, v7, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v4, v50, v4, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(3)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v84
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(2)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v85
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v86
+; GFX11-NEXT: v_perm_b32 v5, v49, v5, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v0, v32, v0, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v87
+; GFX11-NEXT: v_perm_b32 v3, v51, v3, 0x5040100
+; GFX11-NEXT: v_perm_b32 v2, v52, v2, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v100, v96, vcc_lo
+; GFX11-NEXT: v_perm_b32 v1, v31, v1, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v15, v16, v15, 0x5040100
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %cmp = icmp eq <32 x i32> %cond, zeroinitializer
+ %select = select <32 x i1> %cmp, <32 x half> %a, <32 x half> %b
+ ret <32 x half> %select
+}
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