[clang] [riscv] Fix for __riscv_v_fixed_vlen in vector mask types (PR #76510)

[via cfe-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff ae0b2633c935950084860e5f6a1c2c3203726489 69bfbb84879b41d4e8e5fbbd51b9b95b0767c460 -- clang/lib/AST/ItaniumMangle.cpp clang/lib/AST/Type.cpp clang/lib/Sema/SemaType.cpp clang/test/Sema/attr-riscv-rvv-vector-bits.c
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index 740564a17a..39ac3701a5 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -8547,7 +8547,6 @@ static void HandleRISCVRVVVectorBitsTypeAttr(QualType &CurType,
     EltSize = 1;
   unsigned MinElts = Info.EC.getKnownMinValue();
 
-
   // The attribute vector size must match -mrvv-vector-bits.
   unsigned ExpectedSize = VScale->first * MinElts * EltSize;
   if (VecSize != ExpectedSize) {

``````````

</details>


https://github.com/llvm/llvm-project/pull/76510