[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

[Yeting Kuo via cfe-commits]

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@@ -0,0 +1,71 @@
+//===------ RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen -*------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
+  RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> {
+  let Inst{15-13} = 0b011;
+  let Inst{12} = 0;
+  let Inst{11-7} = rs1val;
+  let Inst{6-2} = 0b00000;
+  let Inst{1-0} = 0b01;
+  let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
----------------
yetingk wrote:

They should use same encoding as some instructions of Zimop, but currently, there is no `mop.r` could be fitted to `sspush` and `sspopchk`. The 24th bit of `sspush` is 0 but the 24th bit of all `mop.r` is 1. The 25th bit of `sspopchk` is 0 but but the 25th bit of all `mop.r` is 1.

ref:
https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/mop-r.adoc
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc


https://github.com/llvm/llvm-project/pull/66043