[clang] [llvm] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)
Eric Biggers via cfe-commits
cfe-commits at lists.llvm.org
Mon Dec 18 16:24:30 PST 2023
https://github.com/ebiggers updated https://github.com/llvm/llvm-project/pull/74213
>From 2de2f4a5496eb98814492fdc269eaeb683d030c2 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Fri, 13 Oct 2023 08:23:02 -0700
Subject: [PATCH] [RISCV] Remove experimental from Vector Crypto extensions
The RISC-V vector crypto extensions have been ratified. This patch
updates the Clang and LLVM support for these extensions to be
non-experimental, while leaving the C intrinsics as experimental since
the C intrinsics are not yet standardized.
---
clang/include/clang/Basic/riscv_vector.td | 18 +++---
.../clang/Support/RISCVVIntrinsicUtils.h | 7 +-
clang/lib/Basic/Targets/RISCV.cpp | 4 ++
clang/lib/Basic/Targets/RISCV.h | 1 +
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 4 ++
clang/lib/Sema/SemaChecking.cpp | 2 +-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 19 +++---
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 2 +-
.../non-policy/non-overloaded/vaesdf.c | 17 +++--
.../non-policy/non-overloaded/vaesdm.c | 17 +++--
.../non-policy/non-overloaded/vaesef.c | 17 +++--
.../non-policy/non-overloaded/vaesem.c | 17 +++--
.../non-policy/non-overloaded/vaeskf1.c | 17 +++--
.../non-policy/non-overloaded/vaeskf2.c | 17 +++--
.../non-policy/non-overloaded/vaesz.c | 17 +++--
.../non-policy/non-overloaded/vandn.c | 18 +++---
.../non-policy/non-overloaded/vbrev.c | 17 +++--
.../non-policy/non-overloaded/vbrev8.c | 18 +++---
.../non-policy/non-overloaded/vclmul.c | 17 +++--
.../non-policy/non-overloaded/vclmulh.c | 17 +++--
.../non-policy/non-overloaded/vclz.c | 17 +++--
.../non-policy/non-overloaded/vcpopv.c | 16 ++++-
.../non-policy/non-overloaded/vctz.c | 17 +++--
.../non-policy/non-overloaded/vghsh.c | 17 +++--
.../non-policy/non-overloaded/vgmul.c | 17 +++--
.../non-policy/non-overloaded/vrev8.c | 18 +++---
.../non-policy/non-overloaded/vrol.c | 18 +++---
.../non-policy/non-overloaded/vror.c | 18 +++---
.../non-policy/non-overloaded/vsha2ch.c | 17 +++--
.../non-policy/non-overloaded/vsha2cl.c | 17 +++--
.../non-policy/non-overloaded/vsha2ms.c | 17 +++--
.../non-policy/non-overloaded/vsm3c.c | 17 +++--
.../non-policy/non-overloaded/vsm3me.c | 17 +++--
.../non-policy/non-overloaded/vsm4k.c | 17 +++--
.../non-policy/non-overloaded/vsm4r.c | 17 +++--
.../non-policy/non-overloaded/vwsll.c | 17 +++--
.../non-policy/overloaded/vaesdf.c | 17 +++--
.../non-policy/overloaded/vaesdm.c | 17 +++--
.../non-policy/overloaded/vaesef.c | 17 +++--
.../non-policy/overloaded/vaesem.c | 17 +++--
.../non-policy/overloaded/vaeskf1.c | 17 +++--
.../non-policy/overloaded/vaeskf2.c | 17 +++--
.../non-policy/overloaded/vaesz.c | 17 +++--
.../non-policy/overloaded/vandn.c | 18 +++---
.../non-policy/overloaded/vbrev.c | 17 +++--
.../non-policy/overloaded/vbrev8.c | 18 +++---
.../non-policy/overloaded/vclmul.c | 17 +++--
.../non-policy/overloaded/vclmulh.c | 17 +++--
.../non-policy/overloaded/vclz.c | 17 +++--
.../non-policy/overloaded/vcpopv.c | 16 ++++-
.../non-policy/overloaded/vctz.c | 17 +++--
.../non-policy/overloaded/vghsh.c | 17 +++--
.../non-policy/overloaded/vgmul.c | 17 +++--
.../non-policy/overloaded/vrev8.c | 18 +++---
.../non-policy/overloaded/vrol.c | 18 +++---
.../non-policy/overloaded/vror.c | 18 +++---
.../non-policy/overloaded/vsha2ch.c | 17 +++--
.../non-policy/overloaded/vsha2cl.c | 17 +++--
.../non-policy/overloaded/vsha2ms.c | 17 +++--
.../non-policy/overloaded/vsm3c.c | 17 +++--
.../non-policy/overloaded/vsm3me.c | 17 +++--
.../non-policy/overloaded/vsm4k.c | 17 +++--
.../non-policy/overloaded/vsm4r.c | 17 +++--
.../non-policy/overloaded/vwsll.c | 17 +++--
.../policy/non-overloaded/vaesdf.c | 17 +++--
.../policy/non-overloaded/vaesdm.c | 17 +++--
.../policy/non-overloaded/vaesef.c | 17 +++--
.../policy/non-overloaded/vaesem.c | 17 +++--
.../policy/non-overloaded/vaeskf1.c | 17 +++--
.../policy/non-overloaded/vaeskf2.c | 17 +++--
.../policy/non-overloaded/vaesz.c | 17 +++--
.../policy/non-overloaded/vandn.c | 18 +++---
.../policy/non-overloaded/vbrev.c | 17 +++--
.../policy/non-overloaded/vbrev8.c | 18 +++---
.../policy/non-overloaded/vclmul.c | 17 +++--
.../policy/non-overloaded/vclmulh.c | 17 +++--
.../policy/non-overloaded/vclz.c | 16 ++++-
.../policy/non-overloaded/vcpopv.c | 16 ++++-
.../policy/non-overloaded/vctz.c | 16 ++++-
.../policy/non-overloaded/vghsh.c | 17 +++--
.../policy/non-overloaded/vgmul.c | 17 +++--
.../policy/non-overloaded/vrev8.c | 18 +++---
.../policy/non-overloaded/vrol.c | 18 +++---
.../policy/non-overloaded/vror.c | 18 +++---
.../policy/non-overloaded/vsha2ch.c | 17 +++--
.../policy/non-overloaded/vsha2cl.c | 17 +++--
.../policy/non-overloaded/vsha2ms.c | 17 +++--
.../policy/non-overloaded/vsm3c.c | 17 +++--
.../policy/non-overloaded/vsm3me.c | 17 +++--
.../policy/non-overloaded/vsm4k.c | 17 +++--
.../policy/non-overloaded/vsm4r.c | 17 +++--
.../policy/non-overloaded/vwsll.c | 17 +++--
.../policy/overloaded/vaesdf.c | 17 +++--
.../policy/overloaded/vaesdm.c | 17 +++--
.../policy/overloaded/vaesef.c | 17 +++--
.../policy/overloaded/vaesem.c | 17 +++--
.../policy/overloaded/vaeskf1.c | 17 +++--
.../policy/overloaded/vaeskf2.c | 17 +++--
.../policy/overloaded/vaesz.c | 17 +++--
.../policy/overloaded/vandn.c | 18 +++---
.../policy/overloaded/vbrev.c | 17 +++--
.../policy/overloaded/vbrev8.c | 18 +++---
.../policy/overloaded/vclmul.c | 17 +++--
.../policy/overloaded/vclmulh.c | 17 +++--
.../policy/overloaded/vclz.c | 16 ++++-
.../policy/overloaded/vcpopv.c | 16 ++++-
.../policy/overloaded/vctz.c | 16 ++++-
.../policy/overloaded/vghsh.c | 17 +++--
.../policy/overloaded/vgmul.c | 17 +++--
.../policy/overloaded/vrev8.c | 18 +++---
.../policy/overloaded/vrol.c | 18 +++---
.../policy/overloaded/vror.c | 18 +++---
.../policy/overloaded/vsha2ch.c | 17 +++--
.../policy/overloaded/vsha2cl.c | 17 +++--
.../policy/overloaded/vsha2ms.c | 17 +++--
.../policy/overloaded/vsm3c.c | 17 +++--
.../policy/overloaded/vsm3me.c | 17 +++--
.../policy/overloaded/vsm4k.c | 17 +++--
.../policy/overloaded/vsm4r.c | 17 +++--
.../policy/overloaded/vwsll.c | 17 +++--
.../vaeskf1-out-of-range.c | 4 +-
.../vaeskf2-out-of-range.c | 4 +-
.../vsm3c-out-of-range.c | 4 +-
.../vsm4k-out-of-range.c | 4 +-
clang/test/Sema/zvk-invalid-vlen.c | 4 +-
clang/test/Sema/zvk-invalid-zvknha.c | 2 +-
clang/utils/TableGen/RISCVVEmitter.cpp | 40 ++++++------
llvm/docs/RISCVUsage.rst | 44 ++++++++++++-
llvm/docs/ReleaseNotes.rst | 5 ++
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++++------
llvm/lib/Target/RISCV/RISCVFeatures.td | 36 ++++++-----
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 2 +-
.../Analysis/CostModel/RISCV/int-bit-manip.ll | 2 +-
llvm/test/CodeGen/RISCV/attributes.ll | 64 +++++++++----------
.../CodeGen/RISCV/rvv/bitreverse-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-bitreverse.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 4 +-
.../rvv/fixed-vectors-shuffle-reverse.ll | 4 +-
.../RISCV/rvv/fixed-vectors-shuffle-rotate.ll | 8 +--
.../CodeGen/RISCV/rvv/fixed-vectors-vrol.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vror.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesdf.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesdm.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesef.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesem.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesz.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vandn.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vbrev.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vbrev8.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vclmul.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vclmulh.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vclz.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vcpopv.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vctz.ll | 4 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 4 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vghsh.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vgmul.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vrev8.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vrol.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vror.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll | 8 +--
llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll | 8 +--
llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll | 8 +--
llvm/test/CodeGen/RISCV/rvv/vsm3c.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsm3me.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsm4k.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsm4r.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vwsll.ll | 4 +-
llvm/test/MC/RISCV/rvv/zvbb-invalid.s | 2 +-
llvm/test/MC/RISCV/rvv/zvbb.s | 8 +--
llvm/test/MC/RISCV/rvv/zvbc.s | 8 +--
llvm/test/MC/RISCV/rvv/zvkb.s | 8 +--
llvm/test/MC/RISCV/rvv/zvkg.s | 8 +--
llvm/test/MC/RISCV/rvv/zvkned.s | 8 +--
llvm/test/MC/RISCV/rvv/zvknh.s | 16 ++---
llvm/test/MC/RISCV/rvv/zvksed.s | 8 +--
llvm/test/MC/RISCV/rvv/zvksh.s | 8 +--
.../Transforms/SLPVectorizer/RISCV/ctpop.ll | 4 +-
.../Transforms/SLPVectorizer/RISCV/fround.ll | 4 +-
llvm/unittests/Support/RISCVISAInfoTest.cpp | 32 +++++-----
201 files changed, 1512 insertions(+), 1064 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 682f1d5c8af68c..f2dde7f540fb74 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2540,7 +2540,7 @@ multiclass RVVSignedWidenBinBuiltinSetVwsll
let UnMaskedPolicyScheme = HasPassthruOperand in {
// zvkb
- let RequiredFeatures = ["Zvkb"] in {
+ let RequiredFeatures = ["Zvkb", "Experimental"] in {
defm vandn : RVVUnsignedBinBuiltinSet;
defm vbrev8 : RVVOutBuiltinSetZvbb;
defm vrev8 : RVVOutBuiltinSetZvbb;
@@ -2549,7 +2549,7 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
}
// zvbb
- let RequiredFeatures = ["Zvbb"] in {
+ let RequiredFeatures = ["Zvbb", "Experimental"] in {
defm vbrev : RVVOutBuiltinSetZvbb;
defm vclz : RVVOutBuiltinSetZvbb;
defm vctz : RVVOutBuiltinSetZvbb;
@@ -2559,7 +2559,7 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
}
// zvbc
- let RequiredFeatures = ["Zvbc"] in {
+ let RequiredFeatures = ["Zvbc", "Experimental"] in {
defm vclmul : RVVInt64BinBuiltinSet;
defm vclmulh : RVVInt64BinBuiltinSet;
}
@@ -2567,13 +2567,13 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
// zvkg
- let RequiredFeatures = ["Zvkg"] in {
+ let RequiredFeatures = ["Zvkg", "Experimental"] in {
defm vghsh : RVVOutOp2BuiltinSetVVZvk;
defm vgmul : RVVOutBuiltinSetZvk<HasVV=1, HasVS=0>;
}
// zvkned
- let RequiredFeatures = ["Zvkned"] in {
+ let RequiredFeatures = ["Zvkned", "Experimental"] in {
defm vaesdf : RVVOutBuiltinSetZvk;
defm vaesdm : RVVOutBuiltinSetZvk;
defm vaesef : RVVOutBuiltinSetZvk;
@@ -2585,28 +2585,28 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
}
// zvknha
- let RequiredFeatures = ["Zvknha"] in {
+ let RequiredFeatures = ["Zvknha", "Experimental"] in {
defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"i">;
defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"i">;
defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"i">;
}
// zvknhb
- let RequiredFeatures = ["Zvknhb"] in {
+ let RequiredFeatures = ["Zvknhb", "Experimental"] in {
defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"il">;
defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"il">;
defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"il">;
}
// zvksed
- let RequiredFeatures = ["Zvksed"] in {
+ let RequiredFeatures = ["Zvksed", "Experimental"] in {
let UnMaskedPolicyScheme = HasPassthruOperand in
defm vsm4k : RVVOutOp1BuiltinSet<"vsm4k", "i", [["vi", "Uv", "UvUvKz"]]>;
defm vsm4r : RVVOutBuiltinSetZvk;
}
// zvksh
- let RequiredFeatures = ["Zvksh"] in {
+ let RequiredFeatures = ["Zvksh", "Experimental"] in {
defm vsm3c : RVVOutOp2BuiltinSetVIZvk;
let UnMaskedPolicyScheme = HasPassthruOperand in
defm vsm3me : RVVOutOp1BuiltinSet<"vsm3me", "i", [["vv", "Uv", "UvUvUv"]]>;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 49ce32553da81e..c525d3443331e0 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -485,7 +485,7 @@ class RVVIntrinsic {
// RVVRequire should be sync'ed with target features, but only
// required features used in riscv_vector.td.
-enum RVVRequire : uint16_t {
+enum RVVRequire : uint32_t {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
@@ -503,8 +503,9 @@ enum RVVRequire : uint16_t {
RVV_REQ_Zvknhb = 1 << 13,
RVV_REQ_Zvksed = 1 << 14,
RVV_REQ_Zvksh = 1 << 15,
+ RVV_REQ_Experimental = 1 << 16,
- LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
+ LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental)
};
// Raw RVV intrinsic info, used to expand later.
@@ -536,7 +537,7 @@ struct RVVIntrinsicRecord {
uint8_t OverloadedSuffixSize;
// Required target features for this intrinsic.
- uint16_t RequiredExtensions;
+ uint32_t RequiredExtensions;
// Supported type, mask of BasicType.
uint8_t TypeRangeMask;
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 60a4e0ed69c34d..685462961ee35a 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -350,6 +350,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
.Case("riscv64", Is64Bit)
.Case("32bit", !Is64Bit)
.Case("64bit", Is64Bit)
+ .Case("experimental", HasExperimental)
.Default(std::nullopt);
if (Result)
return *Result;
@@ -382,6 +383,9 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
+ if (llvm::is_contained(Features, "+experimental"))
+ HasExperimental = true;
+
return true;
}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index a893cae914ce03..f98c88cd45f831 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@ class RISCVTargetInfo : public TargetInfo {
private:
bool FastUnalignedAccess;
+ bool HasExperimental = false;
public:
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0b696111e7d712..25b43cefce6b57 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -45,6 +45,10 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
(*ISAInfo)->toFeatures(
Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
/*AddAllExtensions=*/true);
+
+ if (EnableExperimentalExtensions)
+ Features.push_back(Args.MakeArgString("+experimental"));
+
return true;
}
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 42e29e43093789..2a69325f029514 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5389,7 +5389,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
QualType Op2Type = TheCall->getArg(1)->getType();
QualType Op3Type = TheCall->getArg(2)->getType();
uint64_t ElemSize = Op1Type->isRVVType(32, false) ? 32 : 64;
- if (ElemSize == 64 && !TI.hasFeature("experimental-zvknhb"))
+ if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
return Diag(TheCall->getBeginLoc(),
diag::err_riscv_type_requires_extension)
<< Op1Type << "zvknhb";
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index e4642e4da016a4..3ed3e619544189 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -206,15 +206,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
{"xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq},
{"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod},
{"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq},
- {"experimental-zvbb", RVV_REQ_Zvbb},
- {"experimental-zvbc", RVV_REQ_Zvbc},
- {"experimental-zvkb", RVV_REQ_Zvkb},
- {"experimental-zvkg", RVV_REQ_Zvkg},
- {"experimental-zvkned", RVV_REQ_Zvkned},
- {"experimental-zvknha", RVV_REQ_Zvknha},
- {"experimental-zvknhb", RVV_REQ_Zvknhb},
- {"experimental-zvksed", RVV_REQ_Zvksed},
- {"experimental-zvksh", RVV_REQ_Zvksh}};
+ {"zvbb", RVV_REQ_Zvbb},
+ {"zvbc", RVV_REQ_Zvbc},
+ {"zvkb", RVV_REQ_Zvkb},
+ {"zvkg", RVV_REQ_Zvkg},
+ {"zvkned", RVV_REQ_Zvkned},
+ {"zvknha", RVV_REQ_Zvknha},
+ {"zvknhb", RVV_REQ_Zvknhb},
+ {"zvksed", RVV_REQ_Zvksed},
+ {"zvksh", RVV_REQ_Zvksh},
+ {"experimental", RVV_REQ_Experimental}};
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
// in RISCVVEmitter.cpp.
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index bb9f7dc7e7e3d4..bf47461b59e0ad 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1217,7 +1217,7 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) {
OS << (int)Record.PrototypeLength << ",";
OS << (int)Record.SuffixLength << ",";
OS << (int)Record.OverloadedSuffixSize << ",";
- OS << (int)Record.RequiredExtensions << ",";
+ OS << Record.RequiredExtensions << ",";
OS << (int)Record.TypeRangeMask << ",";
OS << (int)Record.Log2LMULMask << ",";
OS << (int)Record.NF << ",";
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
index 7073c65233f65f..76a9ddc0d52946 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
index 1b66240e9f2fcb..468c3f18378d3c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
index c04092a5d9872a..bc6a17e4b6f0fb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
index 88c33d87212fef..e0e1662b76f9cb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
index 3ef9aa473fcc2e..4b3d247ac28093 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
index 94536358d51b06..9249057886c2fc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
index bad34e2eb44140..0700b60fa63995 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
index 4901b9bb4fdf64..1154ee27fe0052 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
index 1e107dc37a2744..6b815bf66ef990 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
index 471a0bb8a1df81..04a1e88a63f574 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
index 54c9aa71f846b2..6137229e273c4c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
index cf10d2566eb627..6c16de1297c06b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
index 1f92b08e3f9598..0910562a9342de 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
index 69eaed4d184e5b..13748be1acc1ac 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
index 26399c1ae7d4d2..9aa10fc518d83f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
index b8fc94b251b936..54a9ebf7a6f5fd 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
index f78ac856cb65ad..8b1000575ab0e3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
index b4187810de9f8f..f520f414b94071 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
index 4f64e5d6dc1fea..1c9a95522c6f47 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
index bf7a252950e1dc..7b37a10bbbaa90 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
index 52002081ddf6f9..6c33dab2ac494b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
index e07a3375e0f970..97f51b41a25396 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
index 0e3be9fdc43669..021349f1d0a01d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
index c6d1fe99d6015c..f6784764893067 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
index cf0fa32a5c3534..e683c0f8a6712b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
index 110dc4c3268ecd..05b164d19d3951 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
index 1e8be7df16e883..f9d855a72d2885 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
index a4c92e1ca05d95..dcc4e7b0e3e1e5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
index 59a01b3fc3ed0d..9c91d2a1192d56 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
index ff6cf16b1143b5..dac9eb38713b4d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
index 8c645d5bd1182d..01875afa525efc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
index 72f2e963433a52..e9a0add21c92d5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
index cc68e546680972..e896fe146fec4c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
index 7c7b141728eb89..7ece17b761d51d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
index 8e596fb1685e10..c80e4ebce5e5b7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
index 0092b9d7980a6f..f3c592ad9960a9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
index 0bb47a67a4bb48..8b9837d8d6a9ba 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
index 637c7139ccac7c..17a1545cdc0551 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
index 46ac3c8a7c0e58..6eebab306bfbba 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
index af323c79680d19..03f8ee06cee4f7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
index 9ea5ac50e3c246..6fd34da34ba4c2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
index d73d656264405e..adb0ac9ee5d79a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
index 4b54f2e41eed12..d35814a09df661 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
index c30dde2e0fbff9..33cf128986c2d2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
index 3a78395e15271b..a6b6de9b067307 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
index c8b3ec5b445f5e..c0cbfeabd14192 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
index 672a35e972ddcb..8775f1394156d4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
index 6d992da031a05e..746ca30300b996 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
index e10541af38be6b..8b4056ae8215d0 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
index c95138b174992e..bf70bd9d583433 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
index b616b49f663a49..c129048f0d2bc6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
index 3a3a8a62a11781..f65689e4301a51 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
index 72837aeb5a66a0..fb4fd66d2a7e12 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
index b25b2ade5806fe..eaf20d83637429 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
index 4eeecb894dda2b..cfc8532835eaa3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
index 6cfdbabb095157..c0a339e6f46cd9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
index c75e3fa6945390..8c18e323f7ceca 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
index b836ff37e58ab1..7566be80e9d93d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
index f5e47a9dee6d83..ddeed6e78be132 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
index 1f5281540d2d71..2bd6350798f643 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
index 1b94f3de632d02..800541d4d42726 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
index 1be7a48707c33a..d55769b63de72a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
index b4686e23c1a279..101efd751f86e3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
index 373e0b98fa326d..250a68503c8374 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
index 872d78295085fa..9ab69bedcfa4ad 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
index 22c4afeea4fcc8..05cf7594876076 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
index 8c65318ccdaf38..a4277ba9fa7d9b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
index cdb4e942b85d25..dc0830d74239ac 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
index 319dae3cfbffbf..fcba519df81300 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
index 61e74dc544ddf1..8a1f2e1beec110 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
index aac53850513d93..3785c92950684a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
index a8deabe51636eb..712d105f4458a8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
index 6a145d47989471..2b2736510b0d61 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
index 075f23d6e4eb70..56565fd604e959 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
index d8777fc06762b0..40a2ed01634488 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
index 4a5d44b5becad2..f37130a365d875 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
index 2f6b10107b2d9c..6cef23f6d933b8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
index 3d7181bd08d101..b21fecc313036e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
index f5477374d3a5b6..8644276915c862 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
index e85ea154d69118..0615be26022f95 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
index fe3d94bc0fddc6..e454c77cb9706b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
index 2ee834858621b4..334758272308bd 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
index 4c8f35161a5d2a..c58f8d22d4601d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
index 9a70fc032f8ade..7cab28445536cc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
index c23649ce655479..34fd46465c34a8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
index f7d66d754fde40..2d0f8e7cafc7e8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
index cf3fab73f076ec..26518b9a709fec 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
index 8a93a7e5440a80..67e13665eea843 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
index 8527cca1523187..d285545eda185b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
index ec6bb1dd498a48..5c73f2e442bfa4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
index de0ceaa0664212..71698175d7b6b7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
index 3f32c1c8e7423e..bf9df04de5dada 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
index b64e9660a97122..39463e8ba83442 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
index f7064acc6af5f8..a0096aaed979e4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
index 6aa9d6bf7f62fa..e4f74a8dde9dac 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
index 34ebdd2c44aa63..d5b992ae345fc3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
index ba7ad3a9f5ec54..79d8c0533bebbc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
index 86b5915efd46a2..02a499d4b67da5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
index 5aed53bafb4d39..7f6a9afaebb069 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
@@ -1,6 +1,18 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
index 59c957debaa7f9..20d04101bf38c9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
index eae136b614321c..81b864a71bf603 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
index 0f9fe962bab397..d0cc4b7020a2a8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
index d21e92248bd104..d2509c30ac66c6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
index b166d1096a0dc3..4f916685d8b7b7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
index baf99c80d3c85d..c9a89ebc5aef7c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
index 05a61a4149053a..81d32a176425fa 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
index b02aa384c850fb..5339c201122fcb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
index e01fcd1c1bc0f1..f88fc4dca19d9e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
index 806d088faf109c..239746c174c2b6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
index cd10883d3c132d..155a935723c69b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
index 06d173ff269c7a..0df390bd0724a0 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
index d6574c28dbef84..ea740944e1c9ee 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh \
+// RUN: -target-feature +experimental \
+// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
index 2062188634c4d6..ba3fa37566740e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvkned -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvkned -target-feature +experimental -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
index a0f8ad76c516af..38907da7d66fd6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvkned -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvkned -target-feature +experimental -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
index a2238f01d23084..988f8aaf98b599 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvksh -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvksh -target-feature +experimental -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
index 56fa9ed53deb45..664b5afb734f62 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvksed -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvksed -target-feature +experimental -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/Sema/zvk-invalid-vlen.c b/clang/test/Sema/zvk-invalid-vlen.c
index a737d620e7aa6e..725c126f28908d 100644
--- a/clang/test/Sema/zvk-invalid-vlen.c
+++ b/clang/test/Sema/zvk-invalid-vlen.c
@@ -1,6 +1,6 @@
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvksh %s -fsyntax-only -verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvkned \
+// RUN: -target-feature +zvksh -target-feature +experimental %s -fsyntax-only -verify
#include <riscv_vector.h>
diff --git a/clang/test/Sema/zvk-invalid-zvknha.c b/clang/test/Sema/zvk-invalid-zvknha.c
index 0ce2e321a175f5..a0a4cf8fb86d5e 100644
--- a/clang/test/Sema/zvk-invalid-zvknha.c
+++ b/clang/test/Sema/zvk-invalid-zvknha.c
@@ -1,5 +1,5 @@
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvknha %s -fsyntax-only -verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvknha %s -fsyntax-only -verify
#include <riscv_vector.h>
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 1fb41805a0473d..da2a885ce8512f 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -46,7 +46,7 @@ struct SemaRecord {
unsigned Log2LMULMask;
// Required extensions for this intrinsic.
- unsigned RequiredExtensions;
+ uint32_t RequiredExtensions;
// Prototype for this intrinsic.
SmallVector<PrototypeDescriptor> Prototype;
@@ -653,24 +653,26 @@ void RVVEmitter::createRVVIntrinsics(
SR.RequiredExtensions = 0;
for (auto RequiredFeature : RequiredFeatures) {
- RVVRequire RequireExt = StringSwitch<RVVRequire>(RequiredFeature)
- .Case("RV64", RVV_REQ_RV64)
- .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
- .Case("Xsfvcp", RVV_REQ_Xsfvcp)
- .Case("Xsfvfnrclipxfqf", RVV_REQ_Xsfvfnrclipxfqf)
- .Case("Xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq)
- .Case("Xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod)
- .Case("Xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq)
- .Case("Zvbb", RVV_REQ_Zvbb)
- .Case("Zvbc", RVV_REQ_Zvbc)
- .Case("Zvkb", RVV_REQ_Zvkb)
- .Case("Zvkg", RVV_REQ_Zvkg)
- .Case("Zvkned", RVV_REQ_Zvkned)
- .Case("Zvknha", RVV_REQ_Zvknha)
- .Case("Zvknhb", RVV_REQ_Zvknhb)
- .Case("Zvksed", RVV_REQ_Zvksed)
- .Case("Zvksh", RVV_REQ_Zvksh)
- .Default(RVV_REQ_None);
+ RVVRequire RequireExt =
+ StringSwitch<RVVRequire>(RequiredFeature)
+ .Case("RV64", RVV_REQ_RV64)
+ .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
+ .Case("Xsfvcp", RVV_REQ_Xsfvcp)
+ .Case("Xsfvfnrclipxfqf", RVV_REQ_Xsfvfnrclipxfqf)
+ .Case("Xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq)
+ .Case("Xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod)
+ .Case("Xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq)
+ .Case("Zvbb", RVV_REQ_Zvbb)
+ .Case("Zvbc", RVV_REQ_Zvbc)
+ .Case("Zvkb", RVV_REQ_Zvkb)
+ .Case("Zvkg", RVV_REQ_Zvkg)
+ .Case("Zvkned", RVV_REQ_Zvkned)
+ .Case("Zvknha", RVV_REQ_Zvknha)
+ .Case("Zvknhb", RVV_REQ_Zvknhb)
+ .Case("Zvksed", RVV_REQ_Zvksed)
+ .Case("Zvksh", RVV_REQ_Zvksh)
+ .Case("Experimental", RVV_REQ_Experimental)
+ .Default(RVV_REQ_None);
assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
SR.RequiredExtensions |= RequireExt;
}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 842ebf45305952..84cc83ef847a57 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -137,12 +137,28 @@ on support follow.
``Zks`` Supported
``Zkt`` Supported
``Zmmul`` Supported
+ ``Zvbb`` Assembly Support
+ ``Zvbc`` Assembly Support
``Zve32x`` (`Partially <#riscv-vlen-32-note>`__) Supported
``Zve32f`` (`Partially <#riscv-vlen-32-note>`__) Supported
``Zve64x`` Supported
``Zve64f`` Supported
``Zve64d`` Supported
``Zvfh`` Supported
+ ``Zvkb`` Assembly Support
+ ``Zvkg`` Assembly Support
+ ``Zvkn`` Assembly Support
+ ``Zvknc`` Assembly Support
+ ``Zvkned`` Assembly Support
+ ``Zvkng`` Assembly Support
+ ``Zvknha`` Assembly Support
+ ``Zvknhb`` Assembly Support
+ ``Zvks`` Assembly Support
+ ``Zvksc`` Assembly Support
+ ``Zvksed`` Assembly Support
+ ``Zvksg`` Assembly Support
+ ``Zvksh`` Assembly Support
+ ``Zvkt`` Assembly Support
``Zvl32b`` (`Partially <#riscv-vlen-32-note>`__) Supported
``Zvl64b`` Supported
``Zvl128b`` Supported
@@ -205,9 +221,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-ztso``
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
-``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
- LLVM implements the `1.0.0-rc2 specification <https://github.com/riscv/riscv-crypto/releases/download/v/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
-
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
Vendor Extensions
@@ -283,3 +296,28 @@ The current vendor extensions supported are:
``XSfcie``
LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.
+
+Experimental C Intrinsics
+=========================
+
+In some cases an extension is non-experimental but the C intrinsics for that
+extension are still experimental. To use C intrinsics for such an extension
+from `clang`, you must add `-menable-experimental-extensions` to the command
+line. This currently applies to the following extensions:
+
+* ``Zvbb``
+* ``Zvbc``
+* ``Zvkb``
+* ``Zvkg``
+* ``Zvkn``
+* ``Zvknc``
+* ``Zvkned``
+* ``Zvkng``
+* ``Zvknha``
+* ``Zvknhb``
+* ``Zvks``
+* ``Zvksc``
+* ``Zvksed``
+* ``Zvksg``
+* ``Zvksh``
+* ``Zvkt``
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 1dd853259c0472..33afa09fcac3da 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -141,6 +141,11 @@ Changes to the RISC-V Backend
* Zihintntl extension version was upgraded to 1.0 and is no longer experimental.
* Intrinsics were added for Zk*, Zbb, and Zbc. See https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#scalar-bit-manipulation-extension-intrinsics
* Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f for RV64.
+* The Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks,
+ Zvksc, Zvksed, Zvksg, Zvksh, and Zvkt extension version was upgraded to 1.0
+ and is no longer experimental. However, the C intrinsics for these extensions
+ are still experimental. To use the C intrinsics for these extensions,
+ ``-menable-experimental-extensions`` needs to be passed to Clang.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 54363e988b702d..137c4ebf2c3cdc 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -145,6 +145,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zmmul", RISCVExtensionVersion{1, 0}},
+ {"zvbb", RISCVExtensionVersion{1, 0}},
+ {"zvbc", RISCVExtensionVersion{1, 0}},
+
{"zve32f", RISCVExtensionVersion{1, 0}},
{"zve32x", RISCVExtensionVersion{1, 0}},
{"zve64d", RISCVExtensionVersion{1, 0}},
@@ -154,6 +157,22 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zvfh", RISCVExtensionVersion{1, 0}},
{"zvfhmin", RISCVExtensionVersion{1, 0}},
+ // vector crypto
+ {"zvkb", RISCVExtensionVersion{1, 0}},
+ {"zvkg", RISCVExtensionVersion{1, 0}},
+ {"zvkn", RISCVExtensionVersion{1, 0}},
+ {"zvknc", RISCVExtensionVersion{1, 0}},
+ {"zvkned", RISCVExtensionVersion{1, 0}},
+ {"zvkng", RISCVExtensionVersion{1, 0}},
+ {"zvknha", RISCVExtensionVersion{1, 0}},
+ {"zvknhb", RISCVExtensionVersion{1, 0}},
+ {"zvks", RISCVExtensionVersion{1, 0}},
+ {"zvksc", RISCVExtensionVersion{1, 0}},
+ {"zvksed", RISCVExtensionVersion{1, 0}},
+ {"zvksg", RISCVExtensionVersion{1, 0}},
+ {"zvksh", RISCVExtensionVersion{1, 0}},
+ {"zvkt", RISCVExtensionVersion{1, 0}},
+
{"zvl1024b", RISCVExtensionVersion{1, 0}},
{"zvl128b", RISCVExtensionVersion{1, 0}},
{"zvl16384b", RISCVExtensionVersion{1, 0}},
@@ -179,27 +198,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"ztso", RISCVExtensionVersion{0, 1}},
- {"zvbb", RISCVExtensionVersion{1, 0}},
- {"zvbc", RISCVExtensionVersion{1, 0}},
-
{"zvfbfmin", RISCVExtensionVersion{0, 8}},
{"zvfbfwma", RISCVExtensionVersion{0, 8}},
-
- // vector crypto
- {"zvkb", RISCVExtensionVersion{1, 0}},
- {"zvkg", RISCVExtensionVersion{1, 0}},
- {"zvkn", RISCVExtensionVersion{1, 0}},
- {"zvknc", RISCVExtensionVersion{1, 0}},
- {"zvkned", RISCVExtensionVersion{1, 0}},
- {"zvkng", RISCVExtensionVersion{1, 0}},
- {"zvknha", RISCVExtensionVersion{1, 0}},
- {"zvknhb", RISCVExtensionVersion{1, 0}},
- {"zvks", RISCVExtensionVersion{1, 0}},
- {"zvksc", RISCVExtensionVersion{1, 0}},
- {"zvksed", RISCVExtensionVersion{1, 0}},
- {"zvksg", RISCVExtensionVersion{1, 0}},
- {"zvksh", RISCVExtensionVersion{1, 0}},
- {"zvkt", RISCVExtensionVersion{1, 0}},
};
static void verifyTables() {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 294927aecb94b8..4d8f7d892bd5b2 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -561,14 +561,14 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
"'Zawrs' (Wait on Reservation Set)">;
def FeatureStdExtZvkb
- : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
+ : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true",
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def FeatureStdExtZvbb
- : SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
+ : SubtargetFeature<"zvbb", "HasStdExtZvbb", "true",
"'Zvbb' (Vector basic bit-manipulation instructions.)",
[FeatureStdExtZvkb]>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
@@ -576,35 +576,35 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
"'Zvbb' (Vector basic bit-manipulation instructions.)">;
def FeatureStdExtZvbc
- : SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
+ : SubtargetFeature<"zvbc", "HasStdExtZvbc", "true",
"'Zvbc' (Vector Carryless Multiplication)">;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
- : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
+ : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true",
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def FeatureStdExtZvkned
- : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
+ : SubtargetFeature<"zvkned", "HasStdExtZvkned", "true",
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def FeatureStdExtZvknha
- : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
+ : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true",
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def FeatureStdExtZvknhb
- : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
+ : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true",
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
[FeatureStdExtZve64x]>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
@@ -616,59 +616,59 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
"'Zvknha' or 'Zvknhb' (Vector SHA-2)">;
def FeatureStdExtZvksed
- : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
+ : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true",
"'Zvksed' (SM4 Block Cipher Instructions)">;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
def FeatureStdExtZvksh
- : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
+ : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true",
"'Zvksh' (SM3 Hash Function Instructions)">;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
def FeatureStdExtZvkt
- : SubtargetFeature<"experimental-zvkt", "HasStdExtZvkt", "true",
+ : SubtargetFeature<"zvkt", "HasStdExtZvkt", "true",
"'Zvkt' (Vector Data-Independent Execution Latency)">;
// Zvk short-hand extensions
def FeatureStdExtZvkn
- : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
+ : SubtargetFeature<"zvkn", "HasStdExtZvkn", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvknc
- : SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
+ : SubtargetFeature<"zvknc", "HasStdExtZvknc", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvkn and Zvbc.",
[FeatureStdExtZvkn, FeatureStdExtZvbc]>;
def FeatureStdExtZvkng
- : SubtargetFeature<"experimental-zvkng", "HasStdExtZvkng", "true",
+ : SubtargetFeature<"zvkng", "HasStdExtZvkng", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvkn and Zvkg.",
[FeatureStdExtZvkn, FeatureStdExtZvkg]>;
def FeatureStdExtZvks
- : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
+ : SubtargetFeature<"zvks", "HasStdExtZvks", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvksc
- : SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",
+ : SubtargetFeature<"zvksc", "HasStdExtZvksc", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvks and Zvbc.",
[FeatureStdExtZvks, FeatureStdExtZvbc]>;
def FeatureStdExtZvksg
- : SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true",
+ : SubtargetFeature<"zvksg", "HasStdExtZvksg", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvks and Zvkg.",
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
@@ -959,6 +959,10 @@ def TuneNoOptimizedZeroStrideLoad
"false", "Hasn't optimized (perform fewer memory operations)"
"zero-stride vector load">;
+def Experimental
+ : SubtargetFeature<"experimental", "HasExperimental",
+ "true", "Experimental intrinsics">;
+
// Some vector hardware implementations do not process all VLEN bits in parallel
// and instead split over multiple cycles. DLEN refers to the datapath width
// that can be done in parallel.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 1ffa78a28d09b8..7c21fb4bcc1ea6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
// This file describes the RISC-V instructions from the standard 'Zvk',
-// Vector Cryptography Instructions extension, version 1.0.0-rc1.
+// Vector Cryptography Instructions extension, version Release 1.0.0.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
index 7798352e6bda77..380f65b19b8fa1 100644
--- a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,NOZVBB
; Vector ctpop exists only under ZVBB
-; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d,+experimental-zvbb -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,ZVBB
+; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d,+zvbb -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,ZVBB
define void @bswap() {
; CHECK-LABEL: 'bswap'
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 25f6e4a56d9324..87609d53cbfa24 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -66,22 +66,22 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s
; RUN: llc -mtriple=riscv32 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHPM %s
; RUN: llc -mtriple=riscv32 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV32ZVKNC %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV32ZVKNG %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvksc %s -o - | FileCheck --check-prefix=RV32ZVKSC %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvknc %s -o - | FileCheck --check-prefix=RV32ZVKNC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvkng %s -o - | FileCheck --check-prefix=RV32ZVKNG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvksc %s -o - | FileCheck --check-prefix=RV32ZVKSC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
@@ -157,22 +157,22 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
; RUN: llc -mtriple=riscv64 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHPM %s
; RUN: llc -mtriple=riscv64 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV64ZVKNC %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV64ZVKNG %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvksc %s -o - | FileCheck --check-prefix=RV64ZVKSC %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvknc %s -o - | FileCheck --check-prefix=RV64ZVKNC %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvkng %s -o - | FileCheck --check-prefix=RV64ZVKNG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvksc %s -o - | FileCheck --check-prefix=RV64ZVKSC %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
index 3514fa66f5886d..19ae26d2424260 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @bitreverse_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-LABEL: bitreverse_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
index 27fd9693b674bd..66eab2f6536224 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.bitreverse.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
index c55399b502471a..d3fce3caf8aef9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
define <vscale x 1 x i16> @bswap_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-LABEL: bswap_nxv1i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index 9952e49116bfcc..800dc7ec388591 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
declare <vscale x 1 x i16> @llvm.vp.bswap.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
index 94cdbc9ed93047..47d65c2593a4cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
@@ -5,8 +5,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @ctlz_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-ZVE64X-LABEL: ctlz_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index 8b43f0115c58cc..e4f030a642f7d1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
index b1415c797ee91d..3a73f1729deddf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @ctpop_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-LABEL: ctpop_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
index d8689ecf05a5e3..2310f85b1fba93 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.ctpop.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index 68ccb2fcbe78bb..b14cde25aa85b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -5,8 +5,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64,RV64F
; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32,RV32D
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64,RV64D
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-ZVE64X-LABEL: cttz_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index dbd2a1fc6eac31..145ce6e917f962 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
index 74a3153b5839dc..1957829b1288ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
@@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,LMULMAX2-RV64
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,LMULMAX1-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @bitreverse_v8i16(ptr %x, ptr %y) {
; RV32-LABEL: bitreverse_v8i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
index 628a3e072abcd0..41f74255c31b06 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
@@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2-RV64
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
define void @bswap_v8i16(ptr %x, ptr %y) {
; CHECK-LABEL: bswap_v8i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index b1d64d2b9a77dc..a4a2cd1333086d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -11,8 +11,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @ctlz_v16i8(ptr %x, ptr %y) nounwind {
; CHECK-LABEL: ctlz_v16i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
index 1f48f9a2ffe648..5e0c99fa1f46e0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
@@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV64
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @ctpop_v16i8(ptr %x, ptr %y) {
; CHECK-LABEL: ctpop_v16i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index 74a2ec954d478b..5afd935935e5d9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -11,8 +11,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @cttz_v16i8(ptr %x, ptr %y) nounwind {
; CHECK-LABEL: cttz_v16i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
index 70b19856fc536c..8f9f1c2729fc71 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
@@ -5,8 +5,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-UNKNOWN
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-256
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-512
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB
;
; VECTOR_REVERSE - masks
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
index 49cd4b85693b60..f67b8ac325c6bf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
define <8 x i1> @shuffle_v8i1_as_i8_1(<8 x i1> %v) {
; CHECK-LABEL: shuffle_v8i1_as_i8_1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
index 99a933985a351d..e719c6f374973a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
index aa63013eec1202..c7c757efc1badc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
declare <1 x i8> @llvm.fshr.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll b/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
index b02c63b29cb8bc..1ad30fa264e0c5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll b/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
index bc1a7c22f373cb..b7a4a11663310a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesef.ll b/llvm/test/CodeGen/RISCV/rvv/vaesef.ll
index 44ab69f0a9a838..bd8a7cb94ab0fb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesef.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesef.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesef.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesem.ll b/llvm/test/CodeGen/RISCV/rvv/vaesem.ll
index 0f35ce017c28c9..21b5e5942e319b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesem.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesem.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesem.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll b/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
index 681ff0d3bf6be3..7988a9f99c85eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll b/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
index ba37f69c380cb9..5abe0821d22996 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesz.ll b/llvm/test/CodeGen/RISCV/rvv/vaesz.ll
index 5c08cf3013365a..ee089f1e77cc35 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesz.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
index f716984599e3f2..a1b1c015369c8c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
define <vscale x 1 x i8> @vandn_vv_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {
; CHECK-LABEL: vandn_vv_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
index c1e85802d3732d..4ff6e5660b25d9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
declare <vscale x 1 x i8> @llvm.vp.and.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
declare <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn.ll b/llvm/test/CodeGen/RISCV/rvv/vandn.ll
index 044b0467d6d20f..a5e29d488da522 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vbrev.ll b/llvm/test/CodeGen/RISCV/rvv/vbrev.ll
index f95e43fb5fcb8c..7e86414990b9b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vbrev.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vbrev.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll b/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
index 64ca9aff6af363..91a65a1b3b1756 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vclmul.ll b/llvm/test/CodeGen/RISCV/rvv/vclmul.ll
index 44aae02cee6f5e..1184d4b96cc5e3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vclmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vclmul.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll b/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
index 673c63837c7758..98befd81ace0c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vclz.ll b/llvm/test/CodeGen/RISCV/rvv/vclz.ll
index aaa760106e91c5..6a9b84c1f43f4f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vclz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vclz.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll b/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
index 99dfc3be9a00c0..523a2a3ec77508 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vctz.ll b/llvm/test/CodeGen/RISCV/rvv/vctz.ll
index 763fac01481172..5089010e2663a2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vctz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vctz.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index b8f2afd194e46d..6ebe8e0954698a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV64 %s
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
; Integers
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 4b5edaa1cd3f7d..5cdbac5ac83d2b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
; Integers
diff --git a/llvm/test/CodeGen/RISCV/rvv/vghsh.ll b/llvm/test/CodeGen/RISCV/rvv/vghsh.ll
index 977386dee8f524..291d505d8faaf7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vghsh.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vghsh.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vgmul.ll b/llvm/test/CodeGen/RISCV/rvv/vgmul.ll
index d4ce44d9eec2be..4498f71008704f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vgmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vgmul.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrev8.ll b/llvm/test/CodeGen/RISCV/rvv/vrev8.ll
index 3a09c971372681..ef58b755ba4cdf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrev8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrev8.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
index 2d8b3647163ea0..fc6af87e473ef3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrol.ll b/llvm/test/CodeGen/RISCV/rvv/vrol.ll
index 05277d1bd718fa..c47afed6f7756a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrol.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
index f8c1bb5194f11b..13a584a6732870 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
declare <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vror.ll b/llvm/test/CodeGen/RISCV/rvv/vror.ll
index 818bb069e798d7..1e8fa86119b6b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vror.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
index 7ee3ffb19c71f6..dd5d48a8d2d40d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
-; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
index 9de122189f4267..f29c74ae69bf65 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
-; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
index ee458daa5fc487..e57baa504da7b7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvknha,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknha,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvknha,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknha,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
-; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+experimental-zvknha 2>&1 \
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s
; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll b/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
index 16d29028c1e30f..17d59682c104fa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll b/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
index ed7f21312c5e22..8d7c2e5975df1b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll b/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
index fe2bb9a77bcc4a..91095da81eeb4e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll b/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
index f9da81eb9575a1..cb836596fdfd1d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
index f45a281c2e00c8..8a0af38f724c4c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
; ==============================================================================
; i32 -> i64
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
index 995adaf6e185ab..e7ac8ee1756415 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64
; ==============================================================================
; i32 -> i64
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll.ll
index 9909fc62d0c80c..9711afb2aafbf0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8(
diff --git a/llvm/test/MC/RISCV/rvv/zvbb-invalid.s b/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
index 46bde3a8ce7029..ca581de02fd603 100644
--- a/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+experimental-zvbb %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+zvbb %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
vwsll.vv v2, v2, v4
diff --git a/llvm/test/MC/RISCV/rvv/zvbb.s b/llvm/test/MC/RISCV/rvv/zvbb.s
index f8c00ceb742c19..41d865e035eaea 100644
--- a/llvm/test/MC/RISCV/rvv/zvbb.s
+++ b/llvm/test/MC/RISCV/rvv/zvbb.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvbb %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvbb %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvbb --no-print-imm-hex - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvbb %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvbb --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvbb %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vbrev.v v10, v9, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvbc.s b/llvm/test/MC/RISCV/rvv/zvbc.s
index 9c1f7873248d90..b32349a2db1335 100644
--- a/llvm/test/MC/RISCV/rvv/zvbc.s
+++ b/llvm/test/MC/RISCV/rvv/zvbc.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve64x --mattr=+experimental-zvbc %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve64x --mattr=+zvbc %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \
-# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvbc - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+zvbc %s \
+# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+zvbc - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+zvbc %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vclmul.vv v10, v9, v8
diff --git a/llvm/test/MC/RISCV/rvv/zvkb.s b/llvm/test/MC/RISCV/rvv/zvkb.s
index 854471b0ce1618..ae2dec18d33ca5 100644
--- a/llvm/test/MC/RISCV/rvv/zvkb.s
+++ b/llvm/test/MC/RISCV/rvv/zvkb.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvkb %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zve32x --mattr=+experimental-zvkb - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkb %s \
+# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+zve32x --mattr=+zvkb - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkb %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vandn.vv v10, v9, v8, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvkg.s b/llvm/test/MC/RISCV/rvv/zvkg.s
index 35b94e96fee549..f2016bc116b656 100644
--- a/llvm/test/MC/RISCV/rvv/zvkg.s
+++ b/llvm/test/MC/RISCV/rvv/zvkg.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvkg %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkg - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkg %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvkg - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkg %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vghsh.vv v10, v9, v8
diff --git a/llvm/test/MC/RISCV/rvv/zvkned.s b/llvm/test/MC/RISCV/rvv/zvkned.s
index 63c13ed4e303a8..e51a9cc562f126 100644
--- a/llvm/test/MC/RISCV/rvv/zvkned.s
+++ b/llvm/test/MC/RISCV/rvv/zvkned.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkned %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvkned %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkned --no-print-imm-hex - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkned %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvkned --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkned %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vaesdf.vv v10, v9
diff --git a/llvm/test/MC/RISCV/rvv/zvknh.s b/llvm/test/MC/RISCV/rvv/zvknh.s
index 9d833a14e419f6..aa8033a5f2170f 100644
--- a/llvm/test/MC/RISCV/rvv/zvknh.s
+++ b/llvm/test/MC/RISCV/rvv/zvknh.s
@@ -1,16 +1,16 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvknha %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+zvknhb %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvknha - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvknha %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvknha - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
-# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvknhb - \
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+zvknhb %s \
+# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+zvknhb - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvknha %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+zvknhb %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
diff --git a/llvm/test/MC/RISCV/rvv/zvksed.s b/llvm/test/MC/RISCV/rvv/zvksed.s
index e0b0be9f5dafc3..87c9713f8c653d 100644
--- a/llvm/test/MC/RISCV/rvv/zvksed.s
+++ b/llvm/test/MC/RISCV/rvv/zvksed.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvksed %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed --no-print-imm-hex - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksed %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvksed --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksed %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vsm4k.vi v10, v9, 7
diff --git a/llvm/test/MC/RISCV/rvv/zvksh.s b/llvm/test/MC/RISCV/rvv/zvksh.s
index 978371fbccb2d0..ca6cb49d30793f 100644
--- a/llvm/test/MC/RISCV/rvv/zvksh.s
+++ b/llvm/test/MC/RISCV/rvv/zvksh.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvksh %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh --no-print-imm-hex - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksh %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvksh --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksh %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vsm3c.vi v10, v9, 7
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/ctpop.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/ctpop.ll
index fa6c83204fbd3f..6502693ada7906 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/ctpop.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/ctpop.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+m,+v | FileCheck %s
; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+m,+v | FileCheck %s
-; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+v,+experimental-zvbb | FileCheck %s
-; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+v,+experimental-zvbb | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+v,+zvbb | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+v,+zvbb | FileCheck %s
define <4 x i8> @ctpop_v4i8(ptr %a) {
; CHECK-LABEL: define <4 x i8> @ctpop_v4i8
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/fround.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/fround.ll
index 9cd0d5d321e2f6..bf5cf1ebf97503 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/fround.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/fround.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+m,+v | FileCheck %s
; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+m,+v | FileCheck %s
-; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+v,+experimental-zvbb | FileCheck %s
-; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+v,+experimental-zvbb | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv32 -mattr=+v,+zvbb | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=riscv64 -mattr=+v,+zvbb | FileCheck %s
define <4 x float> @rint_v4f32(ptr %a) {
; CHECK-LABEL: define <4 x float> @rint_v4f32(
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 3de14907899eb6..ac24831cdaa180 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -683,6 +683,8 @@ R"(All available -march extensions for RISC-V
zksed 1.0
zksh 1.0
zkt 1.0
+ zvbb 1.0
+ zvbc 1.0
zve32f 1.0
zve32x 1.0
zve64d 1.0
@@ -690,6 +692,20 @@ R"(All available -march extensions for RISC-V
zve64x 1.0
zvfh 1.0
zvfhmin 1.0
+ zvkb 1.0
+ zvkg 1.0
+ zvkn 1.0
+ zvknc 1.0
+ zvkned 1.0
+ zvkng 1.0
+ zvknha 1.0
+ zvknhb 1.0
+ zvks 1.0
+ zvksc 1.0
+ zvksed 1.0
+ zvksg 1.0
+ zvksh 1.0
+ zvkt 1.0
zvl1024b 1.0
zvl128b 1.0
zvl16384b 1.0
@@ -741,24 +757,8 @@ Experimental extensions
zacas 1.0
zfbfmin 0.8
ztso 0.1
- zvbb 1.0
- zvbc 1.0
zvfbfmin 0.8
zvfbfwma 0.8
- zvkb 1.0
- zvkg 1.0
- zvkn 1.0
- zvknc 1.0
- zvkned 1.0
- zvkng 1.0
- zvknha 1.0
- zvknhb 1.0
- zvks 1.0
- zvksc 1.0
- zvksed 1.0
- zvksg 1.0
- zvksh 1.0
- zvkt 1.0
Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
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