[mlir] [clang] [llvm] [AMDGPU] - Add address space for strided buffers (PR #74471)

[Krzysztof Drewniak via cfe-commits]

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@@ -864,6 +865,16 @@ supported for the ``amdgcn`` target.
   (bits `127:96`). The specific interpretation of these fields varies by the
   target architecture and is detailed in the ISA descriptions.
 
+**Buffer Strided Pointer**
+  The buffer index pointer is an experimental address space. It is supposed to
+  model a 128-bit buffer descriptor and a 32-bit offset, like the **Buffer Fat
+  Pointer**. Additionally, it contains an index into the buffer, which
+  allows the direct addressing of structured elements.
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krzysz00 wrote:

Document the order of the fields please

https://github.com/llvm/llvm-project/pull/74471