[clang] [Clang][SVE2.1] Add intrinsics for `WHILEcc` resulting in predicate pair (PR #75107)

[Kerry McLaughlin via cfe-commits]

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@@ -1341,6 +1341,26 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNon
 def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile]>;
 }
 
+let TargetGuard = "sve2p1|sme2"  in {
+  def SVWHILEGE_S64_X2 : SInst<"svwhilege_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilege_x2">;
+  def SVWHILEGT_S64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilegt_x2">;
+  def SVWHILEHI_S64_X2 : SInst<"svwhilehi_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilehi_x2">;
+  def SVWHILEHS_S64_X2 : SInst<"svwhilehs_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilehs_x2">;
+  def SVWHILELE_S64_X2 : SInst<"svwhilele_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilele_x2">;
+  def SVWHILELO_S64_X2 : SInst<"svwhilelo_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilelo_x2">;
+  def SVWHILELS_S64_X2 : SInst<"svwhilels_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilels_x2">;
+  def SVWHILELT_S64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2ll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilelt_x2">;
+
+  def SVWHILEGE_U64_X2 : SInst<"svwhilege_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilege_x2">;
+  def SVWHILEGT_U64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilegt_x2">;
+  def SVWHILEHI_U64_X2 : SInst<"svwhilehi_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilehi_x2">;
+  def SVWHILEHS_U64_X2 : SInst<"svwhilehs_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilehs_x2">;
+  def SVWHILELE_U64_X2 : SInst<"svwhilele_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilele_x2">;
+  def SVWHILELO_U64_X2 : SInst<"svwhilelo_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilelo_x2">;
+  def SVWHILELS_U64_X2 : SInst<"svwhilels_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilels_x2">;
+  def SVWHILELT_U64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2nn", "PcPsPiPl",     MergeNone, "aarch64_sve_whilelt_x2">;
+}
----------------
kmclaughlin-arm wrote:

Hi @momchil-velikov,
There were some changes made to the SME2 ACLE recently which included unifying the svwhile signed/unsigned builtins to use the same mnemonics (see https://github.com/ARM-software/acle/pull/217/commits/cdaf16f2fbe329f8951acfe11a6ae227f753d521).
I believe these changes should be applied for SVE2p1 as well?

https://github.com/llvm/llvm-project/pull/75107