[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
Yeting Kuo via cfe-commits
cfe-commits at lists.llvm.org
Mon Dec 11 21:53:16 PST 2023
https://github.com/yetingk updated https://github.com/llvm/llvm-project/pull/66043
>From 834bb96261b3e7b65a0bbd8f2651c3d307f1de79 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/6] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +++++
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++++++++++++++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20 ++++
llvm/test/MC/RISCV/rv32zicfiss-valid.s | 103 ++++++++++++++++++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20 ++++
llvm/test/MC/RISCV/rv64zicfiss-valid.s | 103 ++++++++++++++++++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 6fc921a8c6ee15..79cf98c2c53b19 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -119,6 +119,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1278,3 +1279,11 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
// RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 65dd0d83448ed1..e3b0c42c0f9855 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -199,6 +199,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.2.0>`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1>`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 6322748430063c..95b326cf559b4d 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -175,6 +175,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+ {"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea0..90c340ccd4f39e 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -359,6 +370,10 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
uint64_t Address, const void *Decoder);
+static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder);
+
#include "RISCVGenDisassemblerTables.inc"
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
@@ -373,6 +388,16 @@ static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
return MCDisassembler::Success;
}
+static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
+ DecodeStatus Result = DecodeGPRRARegisterClass(Inst, Rs1, Address, Decoder);
+ (void)Result;
+ assert(Result == MCDisassembler::Success && "Invalid register");
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
@@ -525,6 +550,10 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"RV32Zdinx table (Double in Integer and rv32)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
"RVZfinx table (Float in Integer)");
+ TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZicfiss) &&
+ !STI.hasFeature(RISCV::Feature64Bit),
+ DecoderTableRV32Zicfiss32,
+ "RV32Zicfiss table (Shadow stack and rv32)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
DecoderTableXVentana32, "Ventana custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 294927aecb94b8..af33e8dffb909c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -79,6 +79,13 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
+def FeatureStdExtZicfiss
+ : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true",
+ "'Zicfiss' (Shadow stack)">;
+def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicfiss),
+ "'Zicfiss' (Shadow stack)">;
+
def FeatureStdExtZifencei
: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
"'Zifencei' (fence.i)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index edc08187d8f775..cd416699d0fac1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2111,14 +2111,15 @@ include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZvk.td"
-// Integer
-include "RISCVInstrInfoZicbo.td"
-include "RISCVInstrInfoZicond.td"
-
// Compressed
include "RISCVInstrInfoC.td"
include "RISCVInstrInfoZc.td"
+// Integer
+include "RISCVInstrInfoZicbo.td"
+include "RISCVInstrInfoZicond.td"
+include "RISCVInstrInfoZicfiss.td"
+
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
new file mode 100644
index 00000000000000..f787a260a8ca9d
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -0,0 +1,86 @@
+//===------ RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen -*------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b00000;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+let DecoderNamespace = "RV32Zicfiss", Predicates = [HasStdExtZicfiss, IsRV32] in
+def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRRA:$rd), (ins), "sslw", "$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b100000011100;
+}
+
+let Predicates = [HasStdExtZicfiss, IsRV64] in
+def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRRA:$rd), (ins), "ssld", "$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b100000011100;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRRA:$rs1), "sspopchk",
+ "$rs1"> {
+ let rd = 0;
+ let imm12 = 0b100000011100;
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSINCP : RVInstI<0b100, OPC_SYSTEM, (outs), (ins), "ssincp", ""> {
+ let imm12 = 0b100000011100;
+ let rs1 = 0b00000;
+ let rd = 0b00000;
+}
+
+def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"> {
+ let imm12 = 0b100000011101;
+ let rs1 = 0b00000;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def SSPUSH : RVInstR<0b1000001, 0b100, OPC_SYSTEM, (outs), (ins GPRRA:$rs2),
+ "sspush", "$rs2"> {
+ let rd = 0b00000;
+ let rs1 = 0b00000;
+}
+} // Predicates = [HasStdExtZicfiss]
+
+let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
+} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
+
+let Predicates = [HasStdExtZicfiss, HasStdExtC], Uses = [SSP], Defs = [SSP],
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def C_SSINCP : RVInst16<(outs), (ins), "c.ssincp", "", [], InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = 0b00011;
+ let Inst{6-2} = 0b00000;
+ let Inst{1-0} = 0b01;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index a3c19115bd3178..24f8d600f1eafc 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -127,6 +127,9 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, RISCV::X27);
}
+ // Shadow stack pointer.
+ markSuperRegs(Reserved, RISCV::SSP);
+
assert(checkAllSuperRegsMarked(Reserved));
return Reserved;
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index c59c9b294d793e..4f863d9e0674f6 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -137,6 +137,8 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
(sequence "X%u", 0, 4))>;
def GPRX0 : GPRRegisterClass<(add X0)>;
+def GPRX1 : GPRRegisterClass<(add X1)>;
+def GPRX5 : GPRRegisterClass<(add X5)>;
def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
+ let RegInfos = XLenRI;
+}
+
// Floating point registers
let RegAltNameIndices = [ABIRegAltName] in {
def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
@@ -591,3 +597,6 @@ foreach m = LMULList in {
// Special registers
def FFLAGS : RISCVReg<0, "fflags">;
def FRM : RISCVReg<0, "frm">;
+
+// Shadow Stack register
+def SSP : RISCVReg<0, "ssp">;
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index aa919f266592f4..6b08e9d817ed43 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -311,3 +311,6 @@
.attribute arch, "rv32i_zicfilp0p2"
# CHECK: attribute 5, "rv32i2p1_zicfilp0p2"
+
+.attribute arch, "rv32i_zicfiss0p3"
+# CHECK: .attribute 5, "rv32i2p1_zicfiss0p3"
diff --git a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
new file mode 100644
index 00000000000000..6b4959043d0180
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
@@ -0,0 +1,20 @@
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+
+# CHECK-ERR: error: invalid operand for instruction
+sslw a0
+
+# CHECK-ERR: error: invalid operand for instruction
+sspopchk a1
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspush t0
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspopchk ra
+
+# CHECK-ERR: error: invalid operand for instruction
+sspush a0
+
+# CHECK-ERR: error: invalid operand for instruction
+ssrdp zero
diff --git a/llvm/test/MC/RISCV/rv32zicfiss-valid.s b/llvm/test/MC/RISCV/rv32zicfiss-valid.s
new file mode 100644
index 00000000000000..46a1d3103afac6
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zicfiss-valid.s
@@ -0,0 +1,103 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: sslw ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sslw x1
+
+# CHECK-ASM-AND-OBJ: sslw ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sslw ra
+
+# CHECK-ASM-AND-OBJ: sslw t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sslw x5
+
+# CHECK-ASM-AND-OBJ: sslw t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sslw t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: ssincp
+# CHECK-ASM: encoding: [0x73,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssincp
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x82]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x82]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssrdp ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xd0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssrdp ra
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspush x1
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspush ra
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspopchk x5
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspopchk t0
+
+# CHECK-ASM-AND-OBJ: c.ssincp
+# CHECK-ASM: encoding: [0x81,0x61]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
+c.ssincp
diff --git a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
new file mode 100644
index 00000000000000..aef5e17e33aff9
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
@@ -0,0 +1,20 @@
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+
+# CHECK-ERR: error: invalid operand for instruction
+ssld a0
+
+# CHECK-ERR: error: invalid operand for instruction
+sspopchk a1
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspush t0
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspopchk ra
+
+# CHECK-ERR: error: invalid operand for instruction
+sspush a0
+
+# CHECK-ERR: error: invalid operand for instruction
+ssrdp zero
diff --git a/llvm/test/MC/RISCV/rv64zicfiss-valid.s b/llvm/test/MC/RISCV/rv64zicfiss-valid.s
new file mode 100644
index 00000000000000..8bba15cc3b22be
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zicfiss-valid.s
@@ -0,0 +1,103 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssld ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssld x1
+
+# CHECK-ASM-AND-OBJ: ssld ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssld ra
+
+# CHECK-ASM-AND-OBJ: ssld t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssld x5
+
+# CHECK-ASM-AND-OBJ: ssld t0
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssld t0
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: ssincp
+# CHECK-ASM: encoding: [0x73,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssincp
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x82]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x82]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssrdp ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xd0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssrdp ra
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspush x1
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspush ra
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspopchk x5
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspopchk t0
+
+# CHECK-ASM-AND-OBJ: c.ssincp
+# CHECK-ASM: encoding: [0x81,0x61]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
+c.ssincp
>From f8d4526bc2fbf5cfd97995b14b6021ea2f18c007 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Tue, 3 Oct 2023 15:51:18 +0800
Subject: [PATCH 2/6] [RISCV] Rename GPRRA to GPRX1X5.
---
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 8 ++++----
llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 90c340ccd4f39e..618f459a961a14 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,9 +74,9 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
-static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
+static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
MCRegister Reg = RISCV::X0 + RegNo;
if (Reg != RISCV::X1 && Reg != RISCV::X5)
return MCDisassembler::Fail;
@@ -392,7 +392,7 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
- DecodeStatus Result = DecodeGPRRARegisterClass(Inst, Rs1, Address, Decoder);
+ DecodeStatus Result = DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
(void)Result;
assert(Result == MCDisassembler::Success && "Invalid register");
return MCDisassembler::Success;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
index f787a260a8ca9d..95864664e43f2a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -26,13 +26,13 @@ class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
let DecoderNamespace = "RV32Zicfiss", Predicates = [HasStdExtZicfiss, IsRV32] in
-def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRRA:$rd), (ins), "sslw", "$rd"> {
+def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "sslw", "$rd"> {
let rs1 = 0;
let imm12 = 0b100000011100;
}
let Predicates = [HasStdExtZicfiss, IsRV64] in
-def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRRA:$rd), (ins), "ssld", "$rd"> {
+def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "ssld", "$rd"> {
let rs1 = 0;
let imm12 = 0b100000011100;
}
@@ -40,7 +40,7 @@ def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRRA:$rd), (ins), "ssld", "$rd"> {
let Predicates = [HasStdExtZicfiss] in {
let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRRA:$rs1), "sspopchk",
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
"$rs1"> {
let rd = 0;
let imm12 = 0b100000011100;
@@ -60,7 +60,7 @@ def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"
} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def SSPUSH : RVInstR<0b1000001, 0b100, OPC_SYSTEM, (outs), (ins GPRRA:$rs2),
+def SSPUSH : RVInstR<0b1000001, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
"sspush", "$rs2"> {
let rd = 0b00000;
let rs1 = 0b00000;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 4f863d9e0674f6..4bd3e420debae0 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -167,7 +167,7 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
-def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
+def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
let RegInfos = XLenRI;
}
>From 555d7faa90ff8d10eb8477954823da3d2e41727f Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Wed, 25 Oct 2023 16:11:08 +0800
Subject: [PATCH 3/6] [RISCV] Address Craig's comment.
This does,
1. Add Defs=[SSP] for sspopchk and sspinc.
2. Use HasStdExtCOrZca for sspinc.
3. Add CompressPat for sspinc/sspush/sspopchk.
4. Add a specific file for compressed zicfiss instruction.
---
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 22 +++++--
llvm/test/MC/RISCV/compressed-zicfiss.s | 63 +++++++++++++++++++
llvm/test/MC/RISCV/rv32zicfiss-valid.s | 29 +--------
llvm/test/MC/RISCV/rv64zicfiss-valid.s | 29 +--------
4 files changed, 83 insertions(+), 60 deletions(-)
create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
index 95864664e43f2a..df2bfd6b9fe771 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -39,14 +39,15 @@ def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "ssld", "$rd">
} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
let Predicates = [HasStdExtZicfiss] in {
-let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
"$rs1"> {
let rd = 0;
let imm12 = 0b100000011100;
-} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let Defs = [SSP] in
def SSINCP : RVInstI<0b100, OPC_SYSTEM, (outs), (ins), "ssincp", ""> {
let imm12 = 0b100000011100;
let rs1 = 0b00000;
@@ -71,12 +72,10 @@ let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
-let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
-} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
-let Predicates = [HasStdExtZicfiss, HasStdExtC], Uses = [SSP], Defs = [SSP],
- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_SSINCP : RVInst16<(outs), (ins), "c.ssincp", "", [], InstFormatOther> {
let Inst{15-13} = 0b011;
let Inst{12} = 0;
@@ -84,3 +83,14 @@ def C_SSINCP : RVInst16<(outs), (ins), "c.ssincp", "", [], InstFormatOther> {
let Inst{6-2} = 0b00000;
let Inst{1-0} = 0b01;
}
+} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
+
+//===----------------------------------------------------------------------===/
+// Compress Instruction tablegen backend.
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
+def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;
+def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;
+def : CompressPat<(SSINCP), (C_SSINCP)>;
+} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s
new file mode 100644
index 00000000000000..f96d5867329bd7
--- /dev/null
+++ b/llvm/test/MC/RISCV/compressed-zicfiss.s
@@ -0,0 +1,63 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# CHECK-ASM-AND-OBJ: c.ssincp
+# CHECK-ASM: encoding: [0x81,0x61]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssincp
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspush x1
+
+# CHECK-ASM-AND-OBJ: c.sspush ra
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspush ra
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspopchk x5
+
+# CHECK-ASM-AND-OBJ: c.sspopchk t0
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.sspopchk t0
+
+# CHECK-ASM-AND-OBJ: c.ssincp
+# CHECK-ASM: encoding: [0x81,0x61]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
+c.ssincp
diff --git a/llvm/test/MC/RISCV/rv32zicfiss-valid.s b/llvm/test/MC/RISCV/rv32zicfiss-valid.s
index 46a1d3103afac6..cac3346fc34d7f 100644
--- a/llvm/test/MC/RISCV/rv32zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/rv32zicfiss-valid.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss < %s \
# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
@@ -76,28 +76,3 @@ sspush t0
# CHECK-ASM: encoding: [0xf3,0x40,0xd0,0x81]
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssrdp ra
-
-# CHECK-ASM-AND-OBJ: c.sspush ra
-# CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspush x1
-
-# CHECK-ASM-AND-OBJ: c.sspush ra
-# CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspush ra
-
-# CHECK-ASM-AND-OBJ: c.sspopchk t0
-# CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspopchk x5
-
-# CHECK-ASM-AND-OBJ: c.sspopchk t0
-# CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspopchk t0
-
-# CHECK-ASM-AND-OBJ: c.ssincp
-# CHECK-ASM: encoding: [0x81,0x61]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
-c.ssincp
diff --git a/llvm/test/MC/RISCV/rv64zicfiss-valid.s b/llvm/test/MC/RISCV/rv64zicfiss-valid.s
index 8bba15cc3b22be..68345b59f16876 100644
--- a/llvm/test/MC/RISCV/rv64zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/rv64zicfiss-valid.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss < %s \
# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
@@ -76,28 +76,3 @@ sspush t0
# CHECK-ASM: encoding: [0xf3,0x40,0xd0,0x81]
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssrdp ra
-
-# CHECK-ASM-AND-OBJ: c.sspush ra
-# CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspush x1
-
-# CHECK-ASM-AND-OBJ: c.sspush ra
-# CHECK-ASM: encoding: [0x81,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspush ra
-
-# CHECK-ASM-AND-OBJ: c.sspopchk t0
-# CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspopchk x5
-
-# CHECK-ASM-AND-OBJ: c.sspopchk t0
-# CHECK-ASM: encoding: [0x81,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.sspopchk t0
-
-# CHECK-ASM-AND-OBJ: c.ssincp
-# CHECK-ASM: encoding: [0x81,0x61]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfiss' (Shadow stack)
-c.ssincp
>From 72ae9e04e35591700caffcf38674875ed6375ac0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Thu, 2 Nov 2023 11:40:31 +0800
Subject: [PATCH 4/6] Bump to 0.3.8.
---
.../RISCV/Disassembler/RISCVDisassembler.cpp | 4 -
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 43 ++------
llvm/test/MC/RISCV/rv32zicfiss-valid.s | 78 --------------
llvm/test/MC/RISCV/rv64zicfiss-valid.s | 78 --------------
llvm/test/MC/RISCV/zicfiss-valid.s | 102 ++++++++++++++++++
5 files changed, 111 insertions(+), 194 deletions(-)
delete mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
delete mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 618f459a961a14..8e7ba6a7029c29 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -550,10 +550,6 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"RV32Zdinx table (Double in Integer and rv32)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
"RVZfinx table (Float in Integer)");
- TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZicfiss) &&
- !STI.hasFeature(RISCV::Feature64Bit),
- DecoderTableRV32Zicfiss32,
- "RV32Zicfiss table (Shadow stack and rv32)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
DecoderTableXVentana32, "Ventana custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
index df2bfd6b9fe771..265f7798d97d44 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -24,44 +24,23 @@ class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
// Instructions
//===----------------------------------------------------------------------===//
-let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-let DecoderNamespace = "RV32Zicfiss", Predicates = [HasStdExtZicfiss, IsRV32] in
-def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "sslw", "$rd"> {
- let rs1 = 0;
- let imm12 = 0b100000011100;
-}
-
-let Predicates = [HasStdExtZicfiss, IsRV64] in
-def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "ssld", "$rd"> {
- let rs1 = 0;
- let imm12 = 0b100000011100;
-}
-} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
-
let Predicates = [HasStdExtZicfiss] in {
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
"$rs1"> {
let rd = 0;
- let imm12 = 0b100000011100;
+ let imm12 = 0b110011011100;
} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-let Defs = [SSP] in
-def SSINCP : RVInstI<0b100, OPC_SYSTEM, (outs), (ins), "ssincp", ""> {
- let imm12 = 0b100000011100;
- let rs1 = 0b00000;
- let rd = 0b00000;
-}
-
def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"> {
- let imm12 = 0b100000011101;
+ let imm12 = 0b110011011100;
let rs1 = 0b00000;
}
} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def SSPUSH : RVInstR<0b1000001, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
+def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
"sspush", "$rs2"> {
let rd = 0b00000;
let rs1 = 0b00000;
@@ -74,17 +53,14 @@ def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
-
-let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def C_SSINCP : RVInst16<(outs), (ins), "c.ssincp", "", [], InstFormatOther> {
- let Inst{15-13} = 0b011;
- let Inst{12} = 0;
- let Inst{11-7} = 0b00011;
- let Inst{6-2} = 0b00000;
- let Inst{1-0} = 0b01;
-}
} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
+let Predicates = [HasStdExtA, HasStdExtZicfiss] in
+defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
+
+let Predicates = [HasStdExtA, HasStdExtZicfiss, IsRV64] in
+defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
+
//===----------------------------------------------------------------------===/
// Compress Instruction tablegen backend.
//===----------------------------------------------------------------------===//
@@ -92,5 +68,4 @@ def C_SSINCP : RVInst16<(outs), (ins), "c.ssincp", "", [], InstFormatOther> {
let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;
def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;
-def : CompressPat<(SSINCP), (C_SSINCP)>;
} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
diff --git a/llvm/test/MC/RISCV/rv32zicfiss-valid.s b/llvm/test/MC/RISCV/rv32zicfiss-valid.s
deleted file mode 100644
index cac3346fc34d7f..00000000000000
--- a/llvm/test/MC/RISCV/rv32zicfiss-valid.s
+++ /dev/null
@@ -1,78 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss -riscv-no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-#
-# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
-
-# CHECK-ASM-AND-OBJ: sslw ra
-# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sslw x1
-
-# CHECK-ASM-AND-OBJ: sslw ra
-# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sslw ra
-
-# CHECK-ASM-AND-OBJ: sslw t0
-# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sslw x5
-
-# CHECK-ASM-AND-OBJ: sslw t0
-# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sslw t0
-
-# CHECK-ASM-AND-OBJ: sspopchk ra
-# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk x1
-
-# CHECK-ASM-AND-OBJ: sspopchk ra
-# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk ra
-
-# CHECK-ASM-AND-OBJ: sspopchk t0
-# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk x5
-
-# CHECK-ASM-AND-OBJ: sspopchk t0
-# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk t0
-
-# CHECK-ASM-AND-OBJ: ssincp
-# CHECK-ASM: encoding: [0x73,0x40,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssincp
-
-# CHECK-ASM-AND-OBJ: sspush ra
-# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush x1
-
-# CHECK-ASM-AND-OBJ: sspush ra
-# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush ra
-
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0x82]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush x5
-
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0x82]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush t0
-
-# CHECK-ASM-AND-OBJ: ssrdp ra
-# CHECK-ASM: encoding: [0xf3,0x40,0xd0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssrdp ra
diff --git a/llvm/test/MC/RISCV/rv64zicfiss-valid.s b/llvm/test/MC/RISCV/rv64zicfiss-valid.s
deleted file mode 100644
index 68345b59f16876..00000000000000
--- a/llvm/test/MC/RISCV/rv64zicfiss-valid.s
+++ /dev/null
@@ -1,78 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss -riscv-no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-#
-# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
-
-# CHECK-ASM-AND-OBJ: ssld ra
-# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssld x1
-
-# CHECK-ASM-AND-OBJ: ssld ra
-# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssld ra
-
-# CHECK-ASM-AND-OBJ: ssld t0
-# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssld x5
-
-# CHECK-ASM-AND-OBJ: ssld t0
-# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssld t0
-
-# CHECK-ASM-AND-OBJ: sspopchk ra
-# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk x1
-
-# CHECK-ASM-AND-OBJ: sspopchk ra
-# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk ra
-
-# CHECK-ASM-AND-OBJ: sspopchk t0
-# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk x5
-
-# CHECK-ASM-AND-OBJ: sspopchk t0
-# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspopchk t0
-
-# CHECK-ASM-AND-OBJ: ssincp
-# CHECK-ASM: encoding: [0x73,0x40,0xc0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssincp
-
-# CHECK-ASM-AND-OBJ: sspush ra
-# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush x1
-
-# CHECK-ASM-AND-OBJ: sspush ra
-# CHECK-ASM: encoding: [0x73,0x40,0x10,0x82]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush ra
-
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0x82]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush x5
-
-# check-asm-and-obj: sspush t0
-# check-asm: encoding: [0x73,0x40,0x50,0x82]
-# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-sspush t0
-
-# CHECK-ASM-AND-OBJ: ssrdp ra
-# CHECK-ASM: encoding: [0xf3,0x40,0xd0,0x81]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssrdp ra
diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
new file mode 100644
index 00000000000000..d72a598824ddbd
--- /dev/null
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -0,0 +1,102 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+experimental-zicfiss -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+experimental-zicfiss < %s \
+# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM-RV64,CHECK-ASM,CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss < %s \
+# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -defsym=RV64=1 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-RV64 %s
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk ra
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk t0
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0xce]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0xce]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0xce]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0xce]
+# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssrdp ra
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0xcd]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
+ssrdp ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap.w a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x48]
+# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.w a4, ra, (s0)
+
+# CHECK-ASM-AND-OBJ: ssamoswap.w.aq a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4c]
+# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.w.aq a4, ra, (s0)
+
+# CHECK-ASM-AND-OBJ: ssamoswap.w.rl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4a]
+# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.w.rl a4, ra, (s0)
+
+# CHECK-ASM-AND-OBJ: ssamoswap.w.aqrl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4e]
+# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.w.aqrl a4, ra, (s0)
+
+.ifdef RV64
+# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d a4, ra, (s0)
+# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x48]
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.d a4, ra, (s0)
+
+# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aq a4, ra, (s0)
+# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4c]
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.d.aq a4, ra, (s0)
+
+# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.rl a4, ra, (s0)
+# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4a]
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.d.rl a4, ra, (s0)
+
+# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aqrl a4, ra, (s0)
+# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4e]
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+ssamoswap.d.aqrl a4, ra, (s0)
+.endif
>From 8409108de685af542157caec8f88f48d6f21e9d9 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Tue, 12 Dec 2023 13:51:37 +0800
Subject: [PATCH 5/6] Fix lit test fails.
---
llvm/test/MC/RISCV/compressed-zicfiss.s | 10 ----------
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 3 ---
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 3 ---
3 files changed, 16 deletions(-)
diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s
index f96d5867329bd7..54893555256d14 100644
--- a/llvm/test/MC/RISCV/compressed-zicfiss.s
+++ b/llvm/test/MC/RISCV/compressed-zicfiss.s
@@ -32,11 +32,6 @@ sspush x1
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
sspush ra
-# CHECK-ASM-AND-OBJ: c.ssincp
-# CHECK-ASM: encoding: [0x81,0x61]
-# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
-ssincp
-
# CHECK-ASM-AND-OBJ: c.sspush ra
# CHECK-ASM: encoding: [0x81,0x60]
# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
@@ -56,8 +51,3 @@ c.sspopchk x5
# CHECK-ASM: encoding: [0x81,0x62]
# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
c.sspopchk t0
-
-# CHECK-ASM-AND-OBJ: c.ssincp
-# CHECK-ASM: encoding: [0x81,0x61]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack)
-c.ssincp
diff --git a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
index 6b4959043d0180..1cedcb97e2e7ff 100644
--- a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s
@@ -1,9 +1,6 @@
# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
-# CHECK-ERR: error: invalid operand for instruction
-sslw a0
-
# CHECK-ERR: error: invalid operand for instruction
sspopchk a1
diff --git a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
index aef5e17e33aff9..1296940455e850 100644
--- a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s
@@ -1,9 +1,6 @@
# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
-# CHECK-ERR: error: invalid operand for instruction
-ssld a0
-
# CHECK-ERR: error: invalid operand for instruction
sspopchk a1
>From 16052b1f96b20950f14bffd53c50324d6c04b317 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Tue, 12 Dec 2023 13:51:59 +0800
Subject: [PATCH 6/6] Bumpt to 0.4
This change let ssamoswap not need A extension.
---
clang/test/Preprocessor/riscv-target-features.c | 6 +++---
llvm/lib/Support/RISCVISAInfo.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 4 ++--
llvm/test/MC/RISCV/attribute-arch.s | 4 ++--
llvm/test/MC/RISCV/zicfiss-valid.s | 16 ++++++++--------
llvm/unittests/Support/RISCVISAInfoTest.cpp | 2 ++
6 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 79cf98c2c53b19..d99b53e0a275e8 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1281,9 +1281,9 @@
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
-// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 95b326cf559b4d..7d22eb982602cf 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -175,7 +175,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
- {"zicfiss", RISCVExtensionVersion{0, 3}},
+ {"zicfiss", RISCVExtensionVersion{0, 4}},
{"zicond", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
index 265f7798d97d44..631f36624bd8f5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
@@ -55,10 +55,10 @@ let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
-let Predicates = [HasStdExtA, HasStdExtZicfiss] in
+let Predicates = [HasStdExtZicfiss] in
defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
-let Predicates = [HasStdExtA, HasStdExtZicfiss, IsRV64] in
+let Predicates = [HasStdExtZicfiss, IsRV64] in
defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
//===----------------------------------------------------------------------===/
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 6b08e9d817ed43..8f13118f088d10 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -312,5 +312,5 @@
.attribute arch, "rv32i_zicfilp0p2"
# CHECK: attribute 5, "rv32i2p1_zicfilp0p2"
-.attribute arch, "rv32i_zicfiss0p3"
-# CHECK: .attribute 5, "rv32i2p1_zicfiss0p3"
+.attribute arch, "rv32i_zicfiss0p4"
+# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4"
diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s
index d72a598824ddbd..fd69d37d7cfa01 100644
--- a/llvm/test/MC/RISCV/zicfiss-valid.s
+++ b/llvm/test/MC/RISCV/zicfiss-valid.s
@@ -61,42 +61,42 @@ ssrdp ra
# CHECK-ASM-AND-OBJ: ssamoswap.w a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x48]
-# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.w a4, ra, (s0)
# CHECK-ASM-AND-OBJ: ssamoswap.w.aq a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4c]
-# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.w.aq a4, ra, (s0)
# CHECK-ASM-AND-OBJ: ssamoswap.w.rl a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4a]
-# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.w.rl a4, ra, (s0)
# CHECK-ASM-AND-OBJ: ssamoswap.w.aqrl a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4e]
-# CHECK-NO-EXT: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.w.aqrl a4, ra, (s0)
.ifdef RV64
# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d a4, ra, (s0)
# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x48]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.d a4, ra, (s0)
# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aq a4, ra, (s0)
# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4c]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.d.aq a4, ra, (s0)
# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.rl a4, ra, (s0)
# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4a]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.d.rl a4, ra, (s0)
# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aqrl a4, ra, (s0)
# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4e]
-# CHECK-NO-EXT-RV64: error: instruction requires the following: 'A' (Atomic Instructions), 'Zicfiss' (Shadow stack)
+# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack)
ssamoswap.d.aqrl a4, ra, (s0)
.endif
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 549964eed55518..34f47a26a4a07d 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -737,6 +737,7 @@ R"(All available -march extensions for RISC-V
Experimental extensions
zicfilp 0.2 This is a long dummy description
+ zicfiss 0.4 This is a long dummy description
zicond 1.0
zacas 1.0
zfbfmin 0.8
@@ -767,6 +768,7 @@ For example, clang -march=rv32i_v1p0)";
StringMap<StringRef> DummyMap;
DummyMap["i"] = "This is a long dummy description";
DummyMap["experimental-zicfilp"] = "This is a long dummy description";
+ DummyMap["experimental-zicfiss"] = "This is a long dummy description";
outs().flush();
testing::internal::CaptureStdout();
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