[clang] [RISCV] Prevent checkRVVTypeSupport from issuing more than 1 diagnostic. (PR #74950)

[Craig Topper via cfe-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/74950

If vector isn't enabled at all, we might hit one of the earlier
diagnostics and the requires Zve32x diagnostic. The Zve32x diagnostic
would be redundant.

This is tsacked on #74949

>From 95fd6615dd54e838f81562f648738feba635a66c Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 9 Dec 2023 12:38:43 -0800
Subject: [PATCH 1/2] [RISCV] Refactor checkRVVTypeSupport to use
 BuiltinVectorTypeInfo.

We can decompose the type into ElementType and MinSize and use
those to perform the checks. This is more efficient than using
isRVVType.

This also fixes a bug that we didn't disallow vbool64_t on Zve32x.
---
 clang/lib/Sema/SemaChecking.cpp             | 21 ++++++++++++---------
 clang/test/Sema/riscv-vector-zve32x-check.c |  8 --------
 clang/test/Sema/riscv-vector-zve64x-check.c |  8 ++++++++
 3 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 5c97346184470a..4df01dd9a6b2af 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6107,25 +6107,28 @@ bool Sema::CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
 
 void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
   const TargetInfo &TI = Context.getTargetInfo();
+
+  ASTContext::BuiltinVectorTypeInfo Info =
+      Context.getBuiltinVectorTypeInfo(Ty->castAs<BuiltinType>());
+  unsigned EltSize = Context.getTypeSize(Info.ElementType);
+  unsigned MinElts = Info.EC.getKnownMinValue();
+
   // (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
   // least zve64x
-  if ((Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) ||
-       Ty->isRVVType(/* ElementCount */ 1)) &&
+  if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
       !TI.hasFeature("zve64x"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
-  if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
-      !TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin"))
+  if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
+      !TI.hasFeature("zvfhmin"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D)
         << Ty << "zvfh or zvfhmin";
-  // Check if enabled zvfbfmin for BFloat16
-  if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ false,
-                    /* IsBFloat */ true) &&
+  if (Info.ElementType->isBFloat16Type() &&
       !TI.hasFeature("experimental-zvfbfmin"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfbfmin";
-  if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
+  if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
       !TI.hasFeature("zve32f"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
-  if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ true) &&
+  if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
       !TI.hasFeature("zve64d"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
   // Given that caller already checked isRVVType() before calling this function,
diff --git a/clang/test/Sema/riscv-vector-zve32x-check.c b/clang/test/Sema/riscv-vector-zve32x-check.c
index a021de8bf31fb4..aff6e477378c46 100644
--- a/clang/test/Sema/riscv-vector-zve32x-check.c
+++ b/clang/test/Sema/riscv-vector-zve32x-check.c
@@ -97,11 +97,3 @@ __rvv_bool32_t vbool32 () { /* expected-error {{RISC-V type '__rvv_bool32_t' req
 
   return b32; /* expected-error {{RISC-V type '__rvv_bool32_t' requires the 'zve32x' extension}} */
 }
-
-__rvv_bool64_t vbool64 () { /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve32x' extension}} */
-  __rvv_bool64_t b64; /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve32x' extension}} */
-
-  (void)b64; /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve32x' extension}} */
-
-  return b64; /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve32x' extension}} */
-}
diff --git a/clang/test/Sema/riscv-vector-zve64x-check.c b/clang/test/Sema/riscv-vector-zve64x-check.c
index 5fb2ad483f63f2..7ef156832702d5 100644
--- a/clang/test/Sema/riscv-vector-zve64x-check.c
+++ b/clang/test/Sema/riscv-vector-zve64x-check.c
@@ -37,3 +37,11 @@ __rvv_int64m1_t foo64() { /* expected-error {{RISC-V type '__rvv_int64m1_t' requ
 
   return i64m1; /* expected-error {{RISC-V type '__rvv_int64m1_t' requires the 'zve64x' extension}} */
 }
+
+__rvv_bool64_t vbool64 () { /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve64x' extension}} */
+  __rvv_bool64_t b64; /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve64x' extension}} */
+
+  (void)b64; /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve64x' extension}} */
+
+  return b64; /* expected-error {{RISC-V type '__rvv_bool64_t' requires the 'zve64x' extension}} */
+}

>From 45b1acc66d1c3cfd87d8031be4aaa8a2870efc9a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 9 Dec 2023 12:46:48 -0800
Subject: [PATCH 2/2] [RISCV] Prevent checkRVVTypeSupport from issuing more
 than 1 diagnostic.

If vector isn't enabled at all, we might hit one of the earlier
diagnostics and the requires Zve32x diagnostic. The Zve32x diagnostic
would be redundant.
---
 clang/lib/Sema/SemaChecking.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 4df01dd9a6b2af..44c3cf01a6d534 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6118,22 +6118,22 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
   if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
       !TI.hasFeature("zve64x"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
-  if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
+  else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
       !TI.hasFeature("zvfhmin"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D)
         << Ty << "zvfh or zvfhmin";
-  if (Info.ElementType->isBFloat16Type() &&
+  else if (Info.ElementType->isBFloat16Type() &&
       !TI.hasFeature("experimental-zvfbfmin"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfbfmin";
-  if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
+  else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
       !TI.hasFeature("zve32f"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
-  if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
+  else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
       !TI.hasFeature("zve64d"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
   // Given that caller already checked isRVVType() before calling this function,
   // if we don't have at least zve32x supported, then we need to emit error.
-  if (!TI.hasFeature("zve32x"))
+  else if (!TI.hasFeature("zve32x"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32x";
 }