[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)
Jonathan Thackray via cfe-commits
cfe-commits at lists.llvm.org
Fri Dec 8 03:20:33 PST 2023
jthackray wrote:
> Going by the page (didn't see a link to a manual, maybe I missed it), MVE and FPU are optional.
>
> "Optional Helium technology (M-profile Vector Extension) supporting up to:" "Optional FPU with support for half precision (fp16), single precision (fp32) and double precision (fp64) floating-point operations."
>
> Is this following a pattern from previous CPUs where these things are optional, but users are expected to pass `+nomve` etc. to disable them? (I don't disagree with that, just want to keep it consistent)
Yes, that's correct. We enable all mandatory and optional architecture extensions, with the exception of crypto.
https://github.com/llvm/llvm-project/pull/74822
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