[llvm] [mlir] [clang] [AMDGPU] - Add address space for strided buffers (PR #74471)

[Nicolai Hähnle via cfe-commits]

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@@ -864,6 +865,17 @@ supported for the ``amdgcn`` target.
   (bits `127:96`). The specific interpretation of these fields varies by the
   target architecture and is detailed in the ISA descriptions.
 
+**Buffer Strided Pointer**
+  The buffer index pointer is an experimental address space. It is supposed to
+  model a 128-bit buffer descriptor and a 32-bit offset, like the **Buffer Fat
+  Pointer**. Additionally, it contains an index into the descriptor, which
+  allows the direct addressing of structured elements.
+
+  The buffer descriptor must be *raw*:
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nhaehnle wrote:

It's the same language as for addrspace 7, and I think it makes sense: it's the raw bits as expected by the hardware.

I recall that the buffer intrinsics have a `swz` bit in their flags -- probably due to some HW issue at some point? I don't remember the details.

https://github.com/llvm/llvm-project/pull/74471