[clang] [llvm] [SystemZ] Support i128 as legal type in VRs (PR #74625)
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Wed Dec 6 09:01:01 PST 2023
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<summary>
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git-clang-format --diff 384f916ea899ea6ac9af4a3fb9d0a5b03937acfe a3e9b3a923df055c5ebe9ec045ed99c909a16dd2 -- clang/lib/Headers/vecintrin.h clang/test/CodeGen/SystemZ/builtins-systemz-error2.c clang/test/CodeGen/SystemZ/builtins-systemz-vector.c clang/test/CodeGen/SystemZ/builtins-systemz-vector2-error.c clang/test/CodeGen/SystemZ/builtins-systemz-vector2.c clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp llvm/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/lib/Target/SystemZ/SystemZISelLowering.h
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<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/clang/lib/Headers/vecintrin.h b/clang/lib/Headers/vecintrin.h
index 1f51e32c0d..886770b262 100644
--- a/clang/lib/Headers/vecintrin.h
+++ b/clang/lib/Headers/vecintrin.h
@@ -8388,8 +8388,8 @@ vec_addc(__vector unsigned long long __a, __vector unsigned long long __b) {
static inline __ATTRS_ai __vector unsigned char
vec_addc_u128(__vector unsigned char __a, __vector unsigned char __b) {
- return (__vector unsigned char)
- __builtin_s390_vaccq((unsigned __int128)__a, (unsigned __int128)__b);
+ return (__vector unsigned char)__builtin_s390_vaccq((unsigned __int128)__a,
+ (unsigned __int128)__b);
}
/*-- vec_adde_u128 ----------------------------------------------------------*/
@@ -8397,9 +8397,8 @@ vec_addc_u128(__vector unsigned char __a, __vector unsigned char __b) {
static inline __ATTRS_ai __vector unsigned char
vec_adde_u128(__vector unsigned char __a, __vector unsigned char __b,
__vector unsigned char __c) {
- return (__vector unsigned char)
- __builtin_s390_vacq((unsigned __int128)__a, (unsigned __int128)__b,
- (unsigned __int128)__c);
+ return (__vector unsigned char)__builtin_s390_vacq(
+ (unsigned __int128)__a, (unsigned __int128)__b, (unsigned __int128)__c);
}
/*-- vec_addec_u128 ---------------------------------------------------------*/
@@ -8407,9 +8406,8 @@ vec_adde_u128(__vector unsigned char __a, __vector unsigned char __b,
static inline __ATTRS_ai __vector unsigned char
vec_addec_u128(__vector unsigned char __a, __vector unsigned char __b,
__vector unsigned char __c) {
- return (__vector unsigned char)
- __builtin_s390_vacccq((unsigned __int128)__a, (unsigned __int128)__b,
- (unsigned __int128)__c);
+ return (__vector unsigned char)__builtin_s390_vacccq(
+ (unsigned __int128)__a, (unsigned __int128)__b, (unsigned __int128)__c);
}
/*-- vec_avg ----------------------------------------------------------------*/
@@ -8512,8 +8510,8 @@ static inline __ATTRS_o_ai __vector unsigned char
vec_gfmsum_accum_128(__vector unsigned long long __a,
__vector unsigned long long __b,
__vector unsigned char __c) {
- return (__vector unsigned char)
- __builtin_s390_vgfmag(__a, __b, (unsigned __int128)__c);
+ return (__vector unsigned char)__builtin_s390_vgfmag(__a, __b,
+ (unsigned __int128)__c);
}
/*-- vec_mladd --------------------------------------------------------------*/
@@ -8805,12 +8803,11 @@ vec_mulo(__vector unsigned int __a, __vector unsigned int __b) {
#if __ARCH__ >= 12
extern __ATTRS_o __vector unsigned char
vec_msum_u128(__vector unsigned long long __a, __vector unsigned long long __b,
- __vector unsigned char __c, int __d)
- __constant_range(__d, 0, 15);
+ __vector unsigned char __c, int __d) __constant_range(__d, 0, 15);
-#define vec_msum_u128(X, Y, Z, W) \
- ((__typeof__((vec_msum_u128)((X), (Y), (Z), (W)))) \
- __builtin_s390_vmslg((X), (Y), (unsigned __int128)(Z), (W)))
+#define vec_msum_u128(X, Y, Z, W) \
+ ((__typeof__((vec_msum_u128)((X), (Y), (Z), (W))))__builtin_s390_vmslg( \
+ (X), (Y), (unsigned __int128)(Z), (W)))
#endif
/*-- vec_sub_u128 -----------------------------------------------------------*/
@@ -8846,8 +8843,8 @@ vec_subc(__vector unsigned long long __a, __vector unsigned long long __b) {
static inline __ATTRS_ai __vector unsigned char
vec_subc_u128(__vector unsigned char __a, __vector unsigned char __b) {
- return (__vector unsigned char)
- __builtin_s390_vscbiq((unsigned __int128)__a, (unsigned __int128)__b);
+ return (__vector unsigned char)__builtin_s390_vscbiq((unsigned __int128)__a,
+ (unsigned __int128)__b);
}
/*-- vec_sube_u128 ----------------------------------------------------------*/
@@ -8855,9 +8852,8 @@ vec_subc_u128(__vector unsigned char __a, __vector unsigned char __b) {
static inline __ATTRS_ai __vector unsigned char
vec_sube_u128(__vector unsigned char __a, __vector unsigned char __b,
__vector unsigned char __c) {
- return (__vector unsigned char)
- __builtin_s390_vsbiq((unsigned __int128)__a, (unsigned __int128)__b,
- (unsigned __int128)__c);
+ return (__vector unsigned char)__builtin_s390_vsbiq(
+ (unsigned __int128)__a, (unsigned __int128)__b, (unsigned __int128)__c);
}
/*-- vec_subec_u128 ---------------------------------------------------------*/
@@ -8865,9 +8861,8 @@ vec_sube_u128(__vector unsigned char __a, __vector unsigned char __b,
static inline __ATTRS_ai __vector unsigned char
vec_subec_u128(__vector unsigned char __a, __vector unsigned char __b,
__vector unsigned char __c) {
- return (__vector unsigned char)
- __builtin_s390_vsbcbiq((unsigned __int128)__a, (unsigned __int128)__b,
- (unsigned __int128)__c);
+ return (__vector unsigned char)__builtin_s390_vsbcbiq(
+ (unsigned __int128)__a, (unsigned __int128)__b, (unsigned __int128)__c);
}
/*-- vec_sum2 ---------------------------------------------------------------*/
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 865f297daa..6abe0b392f 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -1187,9 +1187,10 @@ void SystemZDAGToDAGISel::loadVectorConstant(
SelectCode(Op.getNode());
}
-SDNode *SystemZDAGToDAGISel::loadPoolVectorConstant(APInt Val, EVT VT, SDLoc DL) {
+SDNode *SystemZDAGToDAGISel::loadPoolVectorConstant(APInt Val, EVT VT,
+ SDLoc DL) {
SDNode *ResNode;
- assert (VT.getSizeInBits() == 128);
+ assert(VT.getSizeInBits() == 128);
SDValue CP = CurDAG->getTargetConstantPool(
ConstantInt::get(Type::getInt128Ty(*CurDAG->getContext()), Val),
@@ -1197,17 +1198,15 @@ SDNode *SystemZDAGToDAGISel::loadPoolVectorConstant(APInt Val, EVT VT, SDLoc DL)
EVT PtrVT = CP.getValueType();
SDValue Ops[] = {
- SDValue(CurDAG->getMachineNode(SystemZ::LARL, DL, PtrVT, CP), 0),
- CurDAG->getTargetConstant(0, DL, PtrVT),
- CurDAG->getRegister(0, PtrVT),
- CurDAG->getEntryNode()
- };
+ SDValue(CurDAG->getMachineNode(SystemZ::LARL, DL, PtrVT, CP), 0),
+ CurDAG->getTargetConstant(0, DL, PtrVT), CurDAG->getRegister(0, PtrVT),
+ CurDAG->getEntryNode()};
ResNode = CurDAG->getMachineNode(SystemZ::VL, DL, VT, MVT::Other, Ops);
// Annotate ResNode with memory operand information so that MachineInstr
// queries work properly. This e.g. gives the register allocation the
// required information for rematerialization.
- MachineFunction& MF = CurDAG->getMachineFunction();
+ MachineFunction &MF = CurDAG->getMachineFunction();
MachineMemOperand *MemOp =
MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
MachineMemOperand::MOLoad, 8, Align(8));
@@ -1618,11 +1617,11 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) {
SDValue Src = Node->getOperand(0);
Src = CurDAG->getNode(ISD::BITCAST, DL, MVT::v16i8, Src);
- uint64_t Bytes[2] = { 0x0706050403020100ULL, 0x0f0e0d0c0b0a0908ULL };
+ uint64_t Bytes[2] = {0x0706050403020100ULL, 0x0f0e0d0c0b0a0908ULL};
SDNode *Mask = loadPoolVectorConstant(APInt(128, Bytes), MVT::v16i8, DL);
- SDValue Ops[] = { Src, Src, SDValue(Mask, 0) };
- SDValue Res = SDValue(CurDAG->getMachineNode(SystemZ::VPERM, DL,
- MVT::v16i8, Ops), 0);
+ SDValue Ops[] = {Src, Src, SDValue(Mask, 0)};
+ SDValue Res = SDValue(
+ CurDAG->getMachineNode(SystemZ::VPERM, DL, MVT::v16i8, Ops), 0);
Res = CurDAG->getNode(ISD::BITCAST, DL, MVT::i128, Res);
SDNode *ResNode = Res.getNode();
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 89b9fc30c4..3347c0101e 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -242,21 +242,21 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
// Handle i128 if legal.
if (isTypeLegal(MVT::i128)) {
// No special instructions for these.
- setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i128, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i128, Expand);
- setOperationAction(ISD::ROTR, MVT::i128, Expand);
- setOperationAction(ISD::ROTL, MVT::i128, Expand);
- setOperationAction(ISD::MUL, MVT::i128, Expand);
- setOperationAction(ISD::MULHS, MVT::i128, Expand);
- setOperationAction(ISD::MULHU, MVT::i128, Expand);
- setOperationAction(ISD::SDIV, MVT::i128, Expand);
- setOperationAction(ISD::UDIV, MVT::i128, Expand);
- setOperationAction(ISD::SREM, MVT::i128, Expand);
- setOperationAction(ISD::UREM, MVT::i128, Expand);
- setOperationAction(ISD::CTLZ, MVT::i128, Expand);
- setOperationAction(ISD::CTTZ, MVT::i128, Expand);
+ setOperationAction(ISD::ROTR, MVT::i128, Expand);
+ setOperationAction(ISD::ROTL, MVT::i128, Expand);
+ setOperationAction(ISD::MUL, MVT::i128, Expand);
+ setOperationAction(ISD::MULHS, MVT::i128, Expand);
+ setOperationAction(ISD::MULHU, MVT::i128, Expand);
+ setOperationAction(ISD::SDIV, MVT::i128, Expand);
+ setOperationAction(ISD::UDIV, MVT::i128, Expand);
+ setOperationAction(ISD::SREM, MVT::i128, Expand);
+ setOperationAction(ISD::UREM, MVT::i128, Expand);
+ setOperationAction(ISD::CTLZ, MVT::i128, Expand);
+ setOperationAction(ISD::CTTZ, MVT::i128, Expand);
// Support addition/subtraction with carry.
setOperationAction(ISD::UADDO, MVT::i128, Custom);
@@ -2840,9 +2840,8 @@ static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
// Use VECTOR TEST UNDER MASK for i128 operations.
if (C.Op0.getValueType() == MVT::i128) {
// We can use VTM for EQ/NE comparisons of x & y against 0.
- if (C.Op0.getOpcode() == ISD::AND &&
- (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
- C.CCMask == SystemZ::CCMASK_CMP_NE)) {
+ if (C.Op0.getOpcode() == ISD::AND && (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
+ C.CCMask == SystemZ::CCMASK_CMP_NE)) {
auto *Mask = dyn_cast<ConstantSDNode>(C.Op1);
if (Mask && Mask->getAPIntValue() == 0) {
C.Opcode = SystemZISD::VTM;
@@ -2945,8 +2944,7 @@ static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
}
// Implement i128 comparison in vector registers.
-static void adjustICmp128(SelectionDAG &DAG, const SDLoc &DL,
- Comparison &C) {
+static void adjustICmp128(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
if (C.Opcode != SystemZISD::ICMP)
return;
if (C.Op0.getValueType() != MVT::i128)
@@ -2969,11 +2967,19 @@ static void adjustICmp128(SelectionDAG &DAG, const SDLoc &DL,
// Normalize other comparisons to GT.
bool Swap = false, Invert = false;
switch (C.CCMask) {
- case SystemZ::CCMASK_CMP_GT: break;
- case SystemZ::CCMASK_CMP_LT: Swap = true; break;
- case SystemZ::CCMASK_CMP_LE: Invert = true; break;
- case SystemZ::CCMASK_CMP_GE: Swap = Invert = true; break;
- default: llvm_unreachable("Invalid integer condition!");
+ case SystemZ::CCMASK_CMP_GT:
+ break;
+ case SystemZ::CCMASK_CMP_LT:
+ Swap = true;
+ break;
+ case SystemZ::CCMASK_CMP_LE:
+ Invert = true;
+ break;
+ case SystemZ::CCMASK_CMP_GE:
+ Swap = Invert = true;
+ break;
+ default:
+ llvm_unreachable("Invalid integer condition!");
}
if (Swap)
std::swap(C.Op0, C.Op1);
@@ -3054,12 +3060,14 @@ static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid,
- cast<ConstantSDNode>(CmpOp1)->getZExtValue(), Cond);
+ cast<ConstantSDNode>(CmpOp1)->getZExtValue(),
+ Cond);
if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid,
- cast<ConstantSDNode>(CmpOp1)->getZExtValue(), Cond);
+ cast<ConstantSDNode>(CmpOp1)->getZExtValue(),
+ Cond);
}
Comparison C(CmpOp0, CmpOp1, Chain);
C.CCMask = CCMaskForCondCode(Cond);
@@ -3478,8 +3486,7 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
// Check for absolute and negative-absolute selections, including those
// where the comparison value is sign-extended (for LPGFR and LNGFR).
// This check supplements the one in DAGCombiner.
- if (C.Opcode == SystemZISD::ICMP &&
- C.CCMask != SystemZ::CCMASK_CMP_EQ &&
+ if (C.Opcode == SystemZISD::ICMP && C.CCMask != SystemZ::CCMASK_CMP_EQ &&
C.CCMask != SystemZ::CCMASK_CMP_NE &&
C.Op1.getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(C.Op1)->getValueSizeInBits(0) <= 64 &&
@@ -4271,7 +4278,8 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
unsigned BaseOp = 0;
unsigned FlagOp = 0;
switch (Op.getOpcode()) {
- default: llvm_unreachable("Unknown instruction!");
+ default:
+ llvm_unreachable("Unknown instruction!");
case ISD::UADDO:
BaseOp = ISD::ADD;
FlagOp = SystemZISD::VACC;
@@ -4359,7 +4367,8 @@ SDValue SystemZTargetLowering::lowerUADDSUBO_CARRY(SDValue Op,
unsigned BaseOp = 0;
unsigned FlagOp = 0;
switch (Op.getOpcode()) {
- default: llvm_unreachable("Unknown instruction!");
+ default:
+ llvm_unreachable("Unknown instruction!");
case ISD::UADDO_CARRY:
BaseOp = SystemZISD::VAC;
FlagOp = SystemZISD::VACCC;
@@ -4905,8 +4914,8 @@ SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getOperand(1), Op.getOperand(2));
case Intrinsic::s390_vaq:
- return DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(),
- Op.getOperand(1), Op.getOperand(2));
+ return DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
+ Op.getOperand(2));
case Intrinsic::s390_vaccb:
case Intrinsic::s390_vacch:
case Intrinsic::s390_vaccf:
@@ -4922,8 +4931,8 @@ SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
case Intrinsic::s390_vsq:
- return DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(),
- Op.getOperand(1), Op.getOperand(2));
+ return DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
+ Op.getOperand(2));
case Intrinsic::s390_vscbib:
case Intrinsic::s390_vscbih:
case Intrinsic::s390_vscbif:
@@ -6781,22 +6790,21 @@ SDValue SystemZTargetLowering::combineLOAD(
SmallVector<SDValue, 2> ArgChains;
for (auto UserAndIndex : Users) {
SDNode *User = UserAndIndex.first;
- unsigned Offset = User->getValueType(0).getStoreSize() * UserAndIndex.second;
- SDValue Ptr =
- DAG.getMemBasePlusOffset(LD->getBasePtr(), TypeSize::getFixed(Offset), DL);
- SDValue EltLoad =
- DAG.getLoad(User->getValueType(0), DL, LD->getChain(), Ptr,
- LD->getPointerInfo().getWithOffset(Offset),
- LD->getOriginalAlign(), LD->getMemOperand()->getFlags(),
- LD->getAAInfo());
+ unsigned Offset =
+ User->getValueType(0).getStoreSize() * UserAndIndex.second;
+ SDValue Ptr = DAG.getMemBasePlusOffset(LD->getBasePtr(),
+ TypeSize::getFixed(Offset), DL);
+ SDValue EltLoad = DAG.getLoad(
+ User->getValueType(0), DL, LD->getChain(), Ptr,
+ LD->getPointerInfo().getWithOffset(Offset), LD->getOriginalAlign(),
+ LD->getMemOperand()->getFlags(), LD->getAAInfo());
DCI.CombineTo(User, EltLoad, true);
ArgChains.push_back(EltLoad.getValue(1));
}
// Collect all chains via TokenFactor.
- SDValue Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
- ArgChains);
+ SDValue Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, ArgChains);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
DCI.AddToWorklist(Chain.getNode());
return SDValue(N, 0);
@@ -6841,7 +6849,8 @@ bool SystemZTargetLowering::canLoadStoreByteSwapped(EVT VT) const {
if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)
return true;
if (Subtarget.hasVectorEnhancements2())
- if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64 || VT == MVT::i128)
+ if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64 ||
+ VT == MVT::i128)
return true;
return false;
}
@@ -6970,16 +6979,14 @@ SDValue SystemZTargetLowering::combineSTORE(
if (isMovedFromParts(Op1, LoPart, HiPart)) {
SDLoc DL(SN);
SDValue Chain0 =
- DAG.getStore(SN->getChain(), DL, HiPart, SN->getBasePtr(),
- SN->getPointerInfo(), SN->getOriginalAlign(),
- SN->getMemOperand()->getFlags(), SN->getAAInfo());
- SDValue Chain1 =
- DAG.getStore(SN->getChain(), DL, LoPart,
- DAG.getObjectPtrOffset(DL, SN->getBasePtr(),
- TypeSize::getFixed(8)),
- SN->getPointerInfo().getWithOffset(8),
- SN->getOriginalAlign(),
- SN->getMemOperand()->getFlags(), SN->getAAInfo());
+ DAG.getStore(SN->getChain(), DL, HiPart, SN->getBasePtr(),
+ SN->getPointerInfo(), SN->getOriginalAlign(),
+ SN->getMemOperand()->getFlags(), SN->getAAInfo());
+ SDValue Chain1 = DAG.getStore(
+ SN->getChain(), DL, LoPart,
+ DAG.getObjectPtrOffset(DL, SN->getBasePtr(), TypeSize::getFixed(8)),
+ SN->getPointerInfo().getWithOffset(8), SN->getOriginalAlign(),
+ SN->getMemOperand()->getFlags(), SN->getAAInfo());
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain0, Chain1);
}
@@ -8321,10 +8328,9 @@ MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
}
// Implement EmitInstrWithCustomInserter for pseudo [SU]Cmp128Hi instruction MI.
-MachineBasicBlock *
-SystemZTargetLowering::emitICmp128Hi(MachineInstr &MI,
- MachineBasicBlock *MBB,
- bool Unsigned) const {
+MachineBasicBlock *SystemZTargetLowering::emitICmp128Hi(MachineInstr &MI,
+ MachineBasicBlock *MBB,
+ bool Unsigned) const {
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
@@ -8335,7 +8341,7 @@ SystemZTargetLowering::emitICmp128Hi(MachineInstr &MI,
Register Op1 = MI.getOperand(1).getReg();
MachineBasicBlock *StartMBB = MBB;
- MachineBasicBlock *JoinMBB = SystemZ::splitBlockAfter(MI, MBB);
+ MachineBasicBlock *JoinMBB = SystemZ::splitBlockAfter(MI, MBB);
MachineBasicBlock *HiEqMBB = SystemZ::emitBlockAfter(StartMBB);
// StartMBB:
@@ -8352,11 +8358,12 @@ SystemZTargetLowering::emitICmp128Hi(MachineInstr &MI,
// JNE JoinMBB
// # fallthrough to HiEqMBB
MBB = StartMBB;
- int HiOpcode = Unsigned? SystemZ::VECLG : SystemZ::VECG;
- BuildMI(MBB, MI.getDebugLoc(), TII->get(HiOpcode))
- .addReg(Op1).addReg(Op0);
+ int HiOpcode = Unsigned ? SystemZ::VECLG : SystemZ::VECG;
+ BuildMI(MBB, MI.getDebugLoc(), TII->get(HiOpcode)).addReg(Op1).addReg(Op0);
BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::BRC))
- .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE).addMBB(JoinMBB);
+ .addImm(SystemZ::CCMASK_ICMP)
+ .addImm(SystemZ::CCMASK_CMP_NE)
+ .addMBB(JoinMBB);
MBB->addSuccessor(JoinMBB);
MBB->addSuccessor(HiEqMBB);
@@ -8373,7 +8380,8 @@ SystemZTargetLowering::emitICmp128Hi(MachineInstr &MI,
MBB = HiEqMBB;
Register Temp = MRI.createVirtualRegister(&SystemZ::VR128BitRegClass);
BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::VCHLGS), Temp)
- .addReg(Op0).addReg(Op1);
+ .addReg(Op0)
+ .addReg(Op1);
MBB->addSuccessor(JoinMBB);
// Mark CC as live-in to JoinMBB.
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index a72fff8c1f..605d24eb9f 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -98,7 +98,12 @@ enum NodeType : unsigned {
// Add/subtract with overflow/carry. These have the same operands as
// the corresponding standard operations, except with the carry flag
// replaced by a condition code value.
- SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY,
+ SADDO,
+ SSUBO,
+ UADDO,
+ USUBO,
+ ADDCARRY,
+ SUBCARRY,
// Set the condition code from a boolean value in operand 0.
// Operand 1 is a mask of all condition-code values that may result of this
@@ -228,11 +233,14 @@ enum NodeType : unsigned {
VSUM,
// Compute carry/borrow indication for add/subtract.
- VACC, VSCBI,
+ VACC,
+ VSCBI,
// Add/subtract with carry/borrow.
- VAC, VSBI,
+ VAC,
+ VSBI,
// Compute carry/borrow indication for add/subtract with carry/borrow.
- VACCC, VSBCBI,
+ VACCC,
+ VSBCBI,
// Compare integer vector operands 0 and 1 to produce the usual 0/-1
// vector result. VICMPE is for equality, VICMPH for "signed greater than"
@@ -373,10 +381,12 @@ enum NodeType : unsigned {
ATOMIC_CMP_SWAP_128,
// Byte swapping load/store. Same operands as regular load/store.
- LRV, STRV,
+ LRV,
+ STRV,
// Element swapping load/store. Same operands as regular load/store.
- VLER, VSTER,
+ VLER,
+ VSTER,
// Prefetch from the second operand using the 4-bit control code in
// the first operand. The code is 1 for a load prefetch and 2 for
``````````
</details>
https://github.com/llvm/llvm-project/pull/74625
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