[llvm] [clang] [AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (PR #72849)

[Sander de Smalen via cfe-commits]

================
@@ -298,3 +298,11 @@ multiclass ZAAddSub<string n_suffix> {
 
 defm SVADD : ZAAddSub<"add">;
 defm SVSUB : ZAAddSub<"sub">;
+
+//
+// Spill and fill of ZT0
+//
+let TargetGuard = "sme2" in {
+  def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;
----------------
sdesmalen-arm wrote:

Just noticed this after you landed it, but LDR does not preserve ZT0 because it's currently modelled as part of ZA.
This will be modelled differently with https://github.com/ARM-software/acle/pull/276, but it would be good to fix the attribute for now.

https://github.com/llvm/llvm-project/pull/72849