[llvm] [clang] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)

via cfe-commits cfe-commits at lists.llvm.org
Sat Dec 2 14:53:35 PST 2023


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Eric Biggers (ebiggers)

<details>
<summary>Changes</summary>

This is an updated version of https://github.com/llvm/llvm-project/pull/69000, which hasn't had activity in a few weeks

---

Patch is 272.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/74213.diff


200 Files Affected:

- (modified) clang/include/clang/Basic/riscv_vector.td (+9-9) 
- (modified) clang/include/clang/Support/RISCVVIntrinsicUtils.h (+3-2) 
- (modified) clang/lib/Basic/Targets/RISCV.cpp (+5) 
- (modified) clang/lib/Basic/Targets/RISCV.h (+1) 
- (modified) clang/lib/Driver/ToolChains/Arch/RISCV.cpp (+4) 
- (modified) clang/lib/Sema/SemaChecking.cpp (+4-4) 
- (modified) clang/lib/Sema/SemaRISCVVectorLookup.cpp (+10-9) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c (+14-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c (+10-8) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c (+10-7) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c (+2-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c (+2-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c (+2-2) 
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c (+2-2) 
- (modified) clang/test/Sema/zvk-invalid-vlen.c (+2-2) 
- (modified) clang/test/Sema/zvk-invalid-zvknha.c (+1-1) 
- (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+20-18) 
- (modified) llvm/docs/RISCVUsage.rst (+16-3) 
- (modified) llvm/docs/ReleaseNotes.rst (+3) 
- (modified) llvm/lib/Support/RISCVISAInfo.cpp (+19-19) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+20-16) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td (+1-1) 
- (modified) llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll (+1-1) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+32-32) 
- (modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll (+4-4) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vaesdf.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vaesdm.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vaesef.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vaesem.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vaesz.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vbrev.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vbrev8.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vclmul.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vclmulh.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vclz.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vcpopv.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vctz.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vghsh.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vgmul.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vrev8.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vrol.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vror.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll (+4-4) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll (+4-4) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll (+4-4) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vsm3c.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vsm3me.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vsm4k.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vsm4r.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vwsll.ll (+2-2) 
- (modified) llvm/test/MC/RISCV/rvv/zvbb-invalid.s (+1-1) 
- (modified) llvm/test/MC/RISCV/rvv/zvbb.s (+4-4) 
- (modified) llvm/test/MC/RISCV/rvv/zvbc.s (+4-4) 
- (modified) llvm/test/MC/RISCV/rvv/zvkb.s (+4-4) 
- (modified) llvm/test/MC/RISCV/rvv/zvkg.s (+4-4) 
- (modified) llvm/test/MC/RISCV/rvv/zvkned.s (+4-4) 
- (modified) llvm/test/MC/RISCV/rvv/zvknh.s (+8-8) 
- (modified) llvm/test/MC/RISCV/rvv/zvksed.s (+4-4) 
- (modified) llvm/test/MC/RISCV/rvv/zvksh.s (+4-4) 
- (modified) llvm/test/Transforms/SLPVectorizer/RISCV/ctpop.ll (+2-2) 
- (modified) llvm/test/Transforms/SLPVectorizer/RISCV/fround.ll (+2-2) 
- (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+16-16) 


``````````diff
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 682f1d5c8af68..f2dde7f540fb7 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2540,7 +2540,7 @@ multiclass RVVSignedWidenBinBuiltinSetVwsll
 
 let UnMaskedPolicyScheme = HasPassthruOperand in {
   // zvkb
-  let RequiredFeatures = ["Zvkb"] in {
+  let RequiredFeatures = ["Zvkb", "Experimental"] in {
     defm vandn   : RVVUnsignedBinBuiltinSet;
     defm vbrev8  : RVVOutBuiltinSetZvbb;
     defm vrev8   : RVVOutBuiltinSetZvbb;
@@ -2549,7 +2549,7 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
   }
 
   // zvbb
-  let RequiredFeatures = ["Zvbb"] in {
+  let RequiredFeatures = ["Zvbb", "Experimental"] in {
     defm vbrev   : RVVOutBuiltinSetZvbb;
     defm vclz    : RVVOutBuiltinSetZvbb;
     defm vctz    : RVVOutBuiltinSetZvbb;
@@ -2559,7 +2559,7 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
   }
 
   // zvbc
-  let RequiredFeatures = ["Zvbc"] in {
+  let RequiredFeatures = ["Zvbc", "Experimental"] in {
     defm vclmul  : RVVInt64BinBuiltinSet;
     defm vclmulh : RVVInt64BinBuiltinSet;
   }
@@ -2567,13 +2567,13 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
 
 let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
   // zvkg
-  let RequiredFeatures = ["Zvkg"] in {
+  let RequiredFeatures = ["Zvkg", "Experimental"] in {
     defm vghsh   : RVVOutOp2BuiltinSetVVZvk;
     defm vgmul   : RVVOutBuiltinSetZvk<HasVV=1, HasVS=0>;
   }
 
   // zvkned
-  let RequiredFeatures = ["Zvkned"] in {
+  let RequiredFeatures = ["Zvkned", "Experimental"] in {
     defm vaesdf  : RVVOutBuiltinSetZvk;
     defm vaesdm  : RVVOutBuiltinSetZvk;
     defm vaesef  : RVVOutBuiltinSetZvk;
@@ -2585,28 +2585,28 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
   }
 
   // zvknha
-  let RequiredFeatures = ["Zvknha"] in {
+  let RequiredFeatures = ["Zvknha", "Experimental"] in {
     defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"i">;
     defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"i">;
     defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"i">;
   }
 
   // zvknhb
-  let RequiredFeatures = ["Zvknhb"] in {
+  let RequiredFeatures = ["Zvknhb", "Experimental"] in {
     defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"il">;
     defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"il">;
     defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"il">;
   }
 
   // zvksed
-  let RequiredFeatures = ["Zvksed"] in {
+  let RequiredFeatures = ["Zvksed", "Experimental"] in {
     let UnMaskedPolicyScheme = HasPassthruOperand in
     defm vsm4k   : RVVOutOp1BuiltinSet<"vsm4k", "i", [["vi", "Uv", "UvUvKz"]]>;
     defm vsm4r   : RVVOutBuiltinSetZvk;
   }
 
   // zvksh
-  let RequiredFeatures = ["Zvksh"] in {
+  let RequiredFeatures = ["Zvksh", "Experimental"] in {
     defm vsm3c   : RVVOutOp2BuiltinSetVIZvk;
     let UnMaskedPolicyScheme = HasPassthruOperand in
     defm vsm3me  : RVVOutOp1BuiltinSet<"vsm3me", "i", [["vv", "Uv", "UvUvUv"]]>;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 49ce32553da81..a86cd89b65ce5 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -485,7 +485,7 @@ class RVVIntrinsic {
 
 // RVVRequire should be sync'ed with target features, but only
 // required features used in riscv_vector.td.
-enum RVVRequire : uint16_t {
+enum RVVRequire : unsigned int {
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
   RVV_REQ_ZvfhminOrZvfh = 1 << 1,
@@ -503,8 +503,9 @@ enum RVVRequire : uint16_t {
   RVV_REQ_Zvknhb = 1 << 13,
   RVV_REQ_Zvksed = 1 << 14,
   RVV_REQ_Zvksh = 1 << 15,
+  RVV_REQ_Experimental = 1 << 16,
 
-  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
+  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental)
 };
 
 // Raw RVV intrinsic info, used to expand later.
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 13f934e994721..ad685cd27d972 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -343,6 +343,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
                     .Case("riscv64", Is64Bit)
                     .Case("32bit", !Is64Bit)
                     .Case("64bit", Is64Bit)
+                    .Case("experimental", HasExperimental)
                     .Default(std::nullopt);
   if (Result)
     return *Result;
@@ -370,6 +371,10 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
     ISAInfo = std::move(*ParseResult);
   }
 
+  if (std::find(Features.begin(), Features.end(), "+experimental") !=
+      Features.end())
+    HasExperimental = true;
+
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();
 
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index a893cae914ce0..6276a355ef09f 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -28,6 +28,7 @@ class RISCVTargetInfo : public TargetInfo {
 protected:
   std::string ABI, CPU;
   std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
+  bool HasExperimental = false;
 
 private:
   bool FastUnalignedAccess;
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 5d990ba78e5cc..c9bcbbf4d3455 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -45,6 +45,10 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
   (*ISAInfo)->toFeatures(
       Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
       /*AddAllExtensions=*/true);
+
+  if (EnableExperimentalExtensions)
+    Features.push_back(Args.MakeArgString("+experimental"));
+
   return true;
 }
 
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 77c8334f3ca25..52b9570bc9846 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5316,10 +5316,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
     QualType Op2Type = TheCall->getArg(1)->getType();
     QualType Op3Type = TheCall->getArg(2)->getType();
     uint64_t ElemSize = Op1Type->isRVVType(32, false) ? 32 : 64;
-    if (ElemSize == 64 && !TI.hasFeature("experimental-zvknhb"))
-      return
-          Diag(TheCall->getBeginLoc(), diag::err_riscv_type_requires_extension)
-              << Op1Type << "experimental-zvknhb";
+    if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
+      return Diag(TheCall->getBeginLoc(),
+                  diag::err_riscv_type_requires_extension)
+             << Op1Type << "zvknhb";
 
     return CheckInvalidVLENandLMUL(TI, TheCall, *this, Op1Type, ElemSize << 2) ||
            CheckInvalidVLENandLMUL(TI, TheCall, *this, Op2Type, ElemSize << 2) ||
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 9a5aecf669a07..a25f17d13880e 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -212,15 +212,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
       {"xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq},
       {"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod},
       {"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq},
-      {"experimental-zvbb", RVV_REQ_Zvbb},
-      {"experimental-zvbc", RVV_REQ_Zvbc},
-      {"experimental-zvkb", RVV_REQ_Zvkb},
-      {"experimental-zvkg", RVV_REQ_Zvkg},
-      {"experimental-zvkned", RVV_REQ_Zvkned},
-      {"experimental-zvknha", RVV_REQ_Zvknha},
-      {"experimental-zvknhb", RVV_REQ_Zvknhb},
-      {"experimental-zvksed", RVV_REQ_Zvksed},
-      {"experimental-zvksh", RVV_REQ_Zvksh}};
+      {"zvbb", RVV_REQ_Zvbb},
+      {"zvbc", RVV_REQ_Zvbc},
+      {"zvkb", RVV_REQ_Zvkb},
+      {"zvkg", RVV_REQ_Zvkg},
+      {"zvkned", RVV_REQ_Zvkned},
+      {"zvknha", RVV_REQ_Zvknha},
+      {"zvknhb", RVV_REQ_Zvknhb},
+      {"zvksed", RVV_REQ_Zvksed},
+      {"zvksh", RVV_REQ_Zvksh},
+      {"experimental", RVV_REQ_Experimental}};
 
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
index 7073c65233f65..76a9ddc0d5294 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
@@ -1,13 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
index 1b66240e9f2fc..468c3f18378d3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
@@ -1,13 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
index c04092a5d9872..bc6a17e4b6f0f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
@@ -1,13 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
index 88c33d87212fe..e0e1662b76f9c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
@@ -1,13 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
index 3ef9aa473fcc2..4b3d247ac2809 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
@@ -1,13 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
index 94536358d51b0..9249057886c2f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
@@ -1,13 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
index bad34e2eb4414..0700b60fa6399 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
@@ -1,13 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
index 4901b9bb4fdf6..1154ee27fe005 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
@@ -1,14 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN:   -target-feature +experimental-zvbb \
-// RUN:   -target-feature +experimental-zvbc \
-// RUN:   -target-feature +experimental-zvkb \
-// RUN:   -target-feature +experimental-zvkg \
-// RUN:   -target-feature +experimental-zvkned \
-// RUN:   -target-feature +experimental-zvknhb \
-// RUN:   -target-feature +experimental-zvksed \
-// RUN:   -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN:   -target-feature +zvbb \
+// RUN:   -target-feature +zvbc \
+// RUN:   -target-feature +zvkb \
+// RUN:   -target-feature +zvkg \
+// RUN:   -target-feature +zvkned \
+// RUN:   -target-feature +zvknhb \
+// RUN:   -target-feature +zvksed \
+// RUN:   -target-feature +zvksh \
+// RUN:   -target-feature +experimental \
+// RUN:   -disable-O0-optnone \
 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
index 1e107dc37a274..6b815bf66ef99 100644
--- ...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/74213


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