[clang] [clang-format] Add space in Verilog tagged unions (PR #71354)

[via cfe-commits]

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@@ -4694,8 +4694,15 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line,
         Left.isOneOf(TT_VerilogDimensionedTypeName, Keywords.kw_function)) {
       return true;
     }
+    // In a tagged union expression, there should be a space after the tag.
+    if (Right.isOneOf(tok::period, Keywords.kw_apostrophe) &&
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sstwcw wrote:

It is on line 363.

https://github.com/llvm/llvm-project/pull/71354