[llvm] [clang] [SME2] Add LUTI2 and LUTI4 double Builtins and Intrinsics (PR #73305)

[via cfe-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 6b87d84ff45d03c244e7511fba9359776ce27977 5aba2f1d2fe34f721a8e85eef6eecc25cb60851f -- clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 455a966ef0..378c3d8e5f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -5114,7 +5114,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
               Node->getValueType(0),
               {AArch64::LUTI4_2ZTZI_B, AArch64::LUTI4_2ZTZI_H,
                AArch64::LUTI4_2ZTZI_S}))
-      // Second Immediate must be <= 3:
+        // Second Immediate must be <= 3:
         SelectMultiVectorLuti<3>(Node, 2, Opc);
       return;
     }

``````````

</details>


https://github.com/llvm/llvm-project/pull/73305