[clang-tools-extra] [llvm] [clang] [AMDGPU] Fix GCNRewritePartialRegUses pass: vector regclass is selected instead of scalar. (PR #69957)
Valery Pykhtin via cfe-commits
cfe-commits at lists.llvm.org
Wed Nov 15 10:12:21 PST 2023
https://github.com/vpykhtin updated https://github.com/llvm/llvm-project/pull/69957
>From 2d850ac8a057685ba9bb9caa64dd06b7be9ce8d2 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: Thu, 19 Oct 2023 17:09:47 +0200
Subject: [PATCH 1/5] update tests
---
.../AMDGPU/rewrite-partial-reg-uses-dbg.mir | 31 +-
.../AMDGPU/rewrite-partial-reg-uses-gen.mir | 3536 ++++++++---------
.../AMDGPU/rewrite-partial-reg-uses.mir | 46 +-
3 files changed, 1806 insertions(+), 1807 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
index 4e1f912a9d6f98e..85d0c054754d03d 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
@@ -7,7 +7,6 @@
unreachable, !dbg !11
}
- ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare void @llvm.dbg.value(metadata, metadata, metadata) #0
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
@@ -36,21 +35,21 @@ name: test_vreg_96_w64
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_96_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec, debug-location !11
- ; CHECK-NEXT: DBG_VALUE %3.sub0, $noreg, !9, !DIExpression(), debug-location !11
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5)
- ; CHECK-NEXT: DBG_VALUE %3.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
- ; CHECK-NEXT: S_NOP 0, implicit %3, debug-location !DILocation(line: 3, column: 1, scope: !5)
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
- ; CHECK-NEXT: DBG_VALUE %4.sub0, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
- ; CHECK-NEXT: DBG_VALUE %4.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
- ; CHECK-NEXT: S_NOP 0, implicit %4, debug-location !DILocation(line: 6, column: 1, scope: !5)
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
- ; CHECK-NEXT: DBG_VALUE %5, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
- ; CHECK-NEXT: DBG_VALUE %5, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
- ; CHECK-NEXT: S_NOP 0, implicit %5, debug-location !DILocation(line: 6, column: 1, scope: !5)
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec, debug-location !11
+ ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_]].sub0, $noreg, !9, !DIExpression(), debug-location !11
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5)
+ ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_]].sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]], debug-location !DILocation(line: 3, column: 1, scope: !5)
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
+ ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_1]].sub0, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
+ ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_1]].sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]], debug-location !DILocation(line: 6, column: 1, scope: !5)
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
+ ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_2]], $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
+ ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_2]], $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]], debug-location !DILocation(line: 6, column: 1, scope: !5)
undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec, debug-location !11
DBG_VALUE %0.sub0, $noreg, !9, !DIExpression(), debug-location !11
%0.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5)
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
index d51e63f92e69141..86434d1f71a5a88 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
@@ -6,26 +6,26 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_composition_vreg_1024
- ; CHECK: undef %5.sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1
- ; CHECK-NEXT: S_NOP 0, implicit %5.sub1_sub2
- ; CHECK-NEXT: undef %6.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %6.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2
- ; CHECK-NEXT: S_NOP 0, implicit %6.sub1_sub2_sub3
- ; CHECK-NEXT: undef %7.sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
- ; CHECK-NEXT: %7.sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3
- ; CHECK-NEXT: S_NOP 0, implicit %7.sub1_sub2_sub3_sub4
- ; CHECK-NEXT: undef %8.sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
- ; CHECK-NEXT: %8.sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %8.sub0_sub1_sub2_sub3_sub4
- ; CHECK-NEXT: S_NOP 0, implicit %8.sub1_sub2_sub3_sub4_sub5
- ; CHECK-NEXT: undef %9.sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
- ; CHECK-NEXT: %9.sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %9.sub0_sub1_sub2_sub3_sub4_sub5
- ; CHECK-NEXT: S_NOP 0, implicit %9.sub2_sub3_sub4_sub5_sub6_sub7
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0_sub1
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1_sub2
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub0_sub1_sub2
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1_sub2_sub3
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub0_sub1_sub2_sub3
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub1_sub2_sub3_sub4
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_3:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub0_sub1_sub2_sub3_sub4
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub1_sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_4:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub0_sub1_sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub2_sub3_sub4_sub5_sub6_sub7
undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
S_NOP 0, implicit %0.sub1_sub2
@@ -97,12 +97,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_96_w64
- ; CHECK: undef %2.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_96 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_96 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -140,15 +140,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_128_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -168,14 +168,14 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_128_w96
- ; CHECK: undef %2.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_128 = V_MOV_B32_e32 02, implicit $exec
@@ -215,15 +215,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_160_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -243,18 +243,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_160_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec
@@ -277,16 +277,16 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_160_w128
- ; CHECK: undef %2.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec
@@ -328,15 +328,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_192_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -356,18 +356,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_192_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec
@@ -390,21 +390,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_192_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec
@@ -430,18 +430,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_192_w160
- ; CHECK: undef %2.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %2.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec
@@ -485,15 +485,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -513,18 +513,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
@@ -547,21 +547,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
@@ -587,24 +587,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
@@ -633,20 +633,20 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_w192
- ; CHECK: undef %2.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %2.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %2.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
@@ -692,15 +692,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -720,18 +720,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
@@ -754,21 +754,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
@@ -794,24 +794,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
@@ -840,27 +840,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_w192
- ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
@@ -914,15 +914,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -942,18 +942,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
@@ -976,21 +976,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
@@ -1016,24 +1016,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
@@ -1062,27 +1062,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_w192
- ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
@@ -1114,24 +1114,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_w256
- ; CHECK: undef %2.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %2.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %2.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %2.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %2.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
@@ -1181,15 +1181,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -1209,18 +1209,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
@@ -1243,21 +1243,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
@@ -1283,24 +1283,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
@@ -1329,27 +1329,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_w192
- ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
@@ -1381,33 +1381,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_w256
- ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
@@ -1467,15 +1467,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -1495,18 +1495,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
@@ -1529,21 +1529,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
@@ -1569,24 +1569,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
@@ -1615,27 +1615,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_w192
- ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
@@ -1667,33 +1667,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_w256
- ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
@@ -1753,15 +1753,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -1781,18 +1781,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
@@ -1815,21 +1815,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
@@ -1855,24 +1855,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
@@ -1901,27 +1901,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_w192
- ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
@@ -1953,33 +1953,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_w256
- ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
@@ -2039,15 +2039,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -2067,18 +2067,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 213, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 213, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
@@ -2101,21 +2101,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 212, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 213, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 212, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 213, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
@@ -2141,24 +2141,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 212, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 213, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 212, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 213, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
@@ -2187,27 +2187,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_w192
- ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 212, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 213, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 212, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 213, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
@@ -2239,33 +2239,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_w256
- ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 212, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 213, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 212, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 213, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
@@ -2325,15 +2325,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_w64
- ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -2353,18 +2353,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_w96
- ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
@@ -2387,21 +2387,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_w128
- ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
@@ -2427,24 +2427,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_w160
- ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 227, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 227, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
@@ -2473,27 +2473,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_w192
- ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 226, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 227, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 226, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 227, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
@@ -2525,33 +2525,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_w256
- ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 224, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 225, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 226, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 227, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 224, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 225, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 226, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 227, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
@@ -2589,57 +2589,57 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_w512
- ; CHECK: undef %3.sub0:vreg_512 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_512 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_512 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_512 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_512 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_512 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_512 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: %3.sub8:vreg_512 = V_MOV_B32_e32 8, implicit $exec
- ; CHECK-NEXT: %3.sub9:vreg_512 = V_MOV_B32_e32 9, implicit $exec
- ; CHECK-NEXT: %3.sub10:vreg_512 = V_MOV_B32_e32 10, implicit $exec
- ; CHECK-NEXT: %3.sub11:vreg_512 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub12:vreg_512 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub13:vreg_512 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub14:vreg_512 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub15:vreg_512 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_512 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_512 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_512 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_512 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_512 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_512 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_512 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_512 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: %4.sub8:vreg_512 = V_MOV_B32_e32 19, implicit $exec
- ; CHECK-NEXT: %4.sub9:vreg_512 = V_MOV_B32_e32 110, implicit $exec
- ; CHECK-NEXT: %4.sub10:vreg_512 = V_MOV_B32_e32 111, implicit $exec
- ; CHECK-NEXT: %4.sub11:vreg_512 = V_MOV_B32_e32 112, implicit $exec
- ; CHECK-NEXT: %4.sub12:vreg_512 = V_MOV_B32_e32 113, implicit $exec
- ; CHECK-NEXT: %4.sub13:vreg_512 = V_MOV_B32_e32 114, implicit $exec
- ; CHECK-NEXT: %4.sub14:vreg_512 = V_MOV_B32_e32 115, implicit $exec
- ; CHECK-NEXT: %4.sub15:vreg_512 = V_MOV_B32_e32 116, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_512 = V_MOV_B32_e32 216, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_512 = V_MOV_B32_e32 217, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_512 = V_MOV_B32_e32 218, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_512 = V_MOV_B32_e32 219, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_512 = V_MOV_B32_e32 220, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_512 = V_MOV_B32_e32 221, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_512 = V_MOV_B32_e32 222, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_512 = V_MOV_B32_e32 223, implicit $exec
- ; CHECK-NEXT: %5.sub8:vreg_512 = V_MOV_B32_e32 224, implicit $exec
- ; CHECK-NEXT: %5.sub9:vreg_512 = V_MOV_B32_e32 225, implicit $exec
- ; CHECK-NEXT: %5.sub10:vreg_512 = V_MOV_B32_e32 226, implicit $exec
- ; CHECK-NEXT: %5.sub11:vreg_512 = V_MOV_B32_e32 227, implicit $exec
- ; CHECK-NEXT: %5.sub12:vreg_512 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub13:vreg_512 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub14:vreg_512 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub15:vreg_512 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_512 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_512 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_512 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_512 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_512 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_512 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_512 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub8:vreg_512 = V_MOV_B32_e32 8, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub9:vreg_512 = V_MOV_B32_e32 9, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub10:vreg_512 = V_MOV_B32_e32 10, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub11:vreg_512 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub12:vreg_512 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub13:vreg_512 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub14:vreg_512 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub15:vreg_512 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_512 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_512 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_512 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_512 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_512 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_512 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_512 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_512 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub8:vreg_512 = V_MOV_B32_e32 19, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub9:vreg_512 = V_MOV_B32_e32 110, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub10:vreg_512 = V_MOV_B32_e32 111, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub11:vreg_512 = V_MOV_B32_e32 112, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub12:vreg_512 = V_MOV_B32_e32 113, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub13:vreg_512 = V_MOV_B32_e32 114, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub14:vreg_512 = V_MOV_B32_e32 115, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub15:vreg_512 = V_MOV_B32_e32 116, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_512 = V_MOV_B32_e32 216, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_512 = V_MOV_B32_e32 217, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_512 = V_MOV_B32_e32 218, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_512 = V_MOV_B32_e32 219, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_512 = V_MOV_B32_e32 220, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_512 = V_MOV_B32_e32 221, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_512 = V_MOV_B32_e32 222, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_512 = V_MOV_B32_e32 223, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub8:vreg_512 = V_MOV_B32_e32 224, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub9:vreg_512 = V_MOV_B32_e32 225, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub10:vreg_512 = V_MOV_B32_e32 226, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub11:vreg_512 = V_MOV_B32_e32 227, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub12:vreg_512 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub13:vreg_512 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub14:vreg_512 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub15:vreg_512 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
@@ -2701,22 +2701,22 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_composition_vreg_1024_align2
- ; CHECK: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4.sub0_sub1_sub2
- ; CHECK-NEXT: S_NOP 0, implicit %4.sub2_sub3_sub4
- ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1_sub2_sub3
- ; CHECK-NEXT: S_NOP 0, implicit %5.sub2_sub3_sub4_sub5
- ; CHECK-NEXT: undef %6.sub0:vreg_224_align2 = V_MOV_B32_e32 32, implicit $exec
- ; CHECK-NEXT: %6.sub2:vreg_224_align2 = V_MOV_B32_e32 34, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2_sub3_sub4
- ; CHECK-NEXT: S_NOP 0, implicit %6.sub2_sub3_sub4_sub5_sub6
- ; CHECK-NEXT: undef %7.sub0:vreg_256_align2 = V_MOV_B32_e32 42, implicit $exec
- ; CHECK-NEXT: %7.sub2:vreg_256_align2 = V_MOV_B32_e32 44, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3_sub4_sub5
- ; CHECK-NEXT: S_NOP 0, implicit %7.sub2_sub3_sub4_sub5_sub6_sub7
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0_sub1_sub2
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub2_sub3_sub4
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub0_sub1_sub2_sub3
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_224_align2 = V_MOV_B32_e32 32, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_224_align2 = V_MOV_B32_e32 34, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub0_sub1_sub2_sub3_sub4
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub2_sub3_sub4_sub5_sub6
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_3:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 42, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 44, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub0_sub1_sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub2_sub3_sub4_sub5_sub6_sub7
undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec
%1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec
S_NOP 0, implicit %1.sub2_sub3_sub4
@@ -2744,10 +2744,10 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_64_align2_w32
- ; CHECK: undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -2761,12 +2761,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_96_align2_w32
- ; CHECK: undef %0.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub2
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub2
undef %0.sub0:vreg_96_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -2784,12 +2784,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_128_align2_w32
- ; CHECK: undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub3
undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -2806,12 +2806,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_128_align2_w64
- ; CHECK: undef %2.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_128_align2 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -2828,12 +2828,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_160_align2_w32
- ; CHECK: undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub4
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub4
undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -2851,14 +2851,14 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_160_align2_w96
- ; CHECK: undef %2.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_160_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_160_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -2877,12 +2877,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_192_align2_w32
- ; CHECK: undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub5
undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -2899,15 +2899,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_192_align2_w64
- ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -2928,16 +2928,16 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_192_align2_w128
- ; CHECK: undef %2.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_192_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -2958,12 +2958,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_align2_w32
- ; CHECK: undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub6
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_224_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub6
undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -2981,18 +2981,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_align2_w96
- ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3016,18 +3016,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_224_align2_w160
- ; CHECK: undef %2.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %2.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3050,12 +3050,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_align2_w32
- ; CHECK: undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub7
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub7
undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -3072,15 +3072,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_align2_w64
- ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -3101,21 +3101,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_align2_w128
- ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3142,20 +3142,20 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_256_align2_w192
- ; CHECK: undef %2.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %2.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %2.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3179,12 +3179,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_align2_w32
- ; CHECK: undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub8
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_288_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub8
undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -3202,18 +3202,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_align2_w96
- ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3237,24 +3237,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_288_align2_w160
- ; CHECK: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3285,12 +3285,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_align2_w32
- ; CHECK: undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub9
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_320_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub9
undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -3307,15 +3307,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_align2_w64
- ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -3336,21 +3336,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_align2_w128
- ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3377,27 +3377,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_align2_w192
- ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3429,24 +3429,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_320_align2_w256
- ; CHECK: undef %2.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %2.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %2.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %2.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %2.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %2.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %2.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %2.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3474,12 +3474,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_align2_w32
- ; CHECK: undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub10
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_352_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub10
undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -3497,18 +3497,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_align2_w96
- ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3532,24 +3532,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_352_align2_w160
- ; CHECK: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_160_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_160_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3580,12 +3580,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_align2_w32
- ; CHECK: undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub11
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_384_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub11
undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -3602,15 +3602,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_align2_w64
- ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 110, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 111, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 110, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 111, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -3631,21 +3631,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_align2_w128
- ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3672,27 +3672,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_align2_w192
- ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3724,33 +3724,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_384_align2_w256
- ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3788,12 +3788,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_align2_w32
- ; CHECK: undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub15
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub15
undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -3810,15 +3810,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_align2_w64
- ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 114, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 115, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 114, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 115, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -3839,21 +3839,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_align2_w128
- ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 112, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 113, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 114, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 115, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 112, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 113, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 114, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 115, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3880,27 +3880,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_align2_w192
- ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 110, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 111, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 112, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 113, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 114, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 115, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 110, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 111, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 112, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 113, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 114, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 115, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3932,33 +3932,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_512_align2_w256
- ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 212, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 213, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 212, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 213, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -3996,12 +3996,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_align2_w32
- ; CHECK: undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
- ; CHECK-NEXT: undef %1.sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
- ; CHECK-NEXT: undef %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub31
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_1024_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub31
undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
S_NOP 0, implicit %0.sub0
@@ -4018,15 +4018,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_align2_w64
- ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
S_NOP 0, implicit %0.sub0_sub1
@@ -4047,21 +4047,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_align2_w128
- ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -4088,27 +4088,27 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_align2_w192
- ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 226, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 227, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 226, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 227, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -4140,33 +4140,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_align2_w256
- ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 224, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 225, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 226, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 227, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 228, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 229, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 230, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 231, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 224, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 225, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 226, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 227, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 228, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 229, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 230, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 231, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -4204,57 +4204,57 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vreg_1024_align2_w512
- ; CHECK: undef %3.sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: %3.sub1:vreg_512_align2 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %3.sub2:vreg_512_align2 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: %3.sub3:vreg_512_align2 = V_MOV_B32_e32 3, implicit $exec
- ; CHECK-NEXT: %3.sub4:vreg_512_align2 = V_MOV_B32_e32 4, implicit $exec
- ; CHECK-NEXT: %3.sub5:vreg_512_align2 = V_MOV_B32_e32 5, implicit $exec
- ; CHECK-NEXT: %3.sub6:vreg_512_align2 = V_MOV_B32_e32 6, implicit $exec
- ; CHECK-NEXT: %3.sub7:vreg_512_align2 = V_MOV_B32_e32 7, implicit $exec
- ; CHECK-NEXT: %3.sub8:vreg_512_align2 = V_MOV_B32_e32 8, implicit $exec
- ; CHECK-NEXT: %3.sub9:vreg_512_align2 = V_MOV_B32_e32 9, implicit $exec
- ; CHECK-NEXT: %3.sub10:vreg_512_align2 = V_MOV_B32_e32 10, implicit $exec
- ; CHECK-NEXT: %3.sub11:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %3.sub12:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: %3.sub13:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec
- ; CHECK-NEXT: %3.sub14:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec
- ; CHECK-NEXT: %3.sub15:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:vreg_512_align2 = V_MOV_B32_e32 116, implicit $exec
- ; CHECK-NEXT: %4.sub1:vreg_512_align2 = V_MOV_B32_e32 117, implicit $exec
- ; CHECK-NEXT: %4.sub2:vreg_512_align2 = V_MOV_B32_e32 118, implicit $exec
- ; CHECK-NEXT: %4.sub3:vreg_512_align2 = V_MOV_B32_e32 119, implicit $exec
- ; CHECK-NEXT: %4.sub4:vreg_512_align2 = V_MOV_B32_e32 120, implicit $exec
- ; CHECK-NEXT: %4.sub5:vreg_512_align2 = V_MOV_B32_e32 121, implicit $exec
- ; CHECK-NEXT: %4.sub6:vreg_512_align2 = V_MOV_B32_e32 122, implicit $exec
- ; CHECK-NEXT: %4.sub7:vreg_512_align2 = V_MOV_B32_e32 123, implicit $exec
- ; CHECK-NEXT: %4.sub8:vreg_512_align2 = V_MOV_B32_e32 124, implicit $exec
- ; CHECK-NEXT: %4.sub9:vreg_512_align2 = V_MOV_B32_e32 125, implicit $exec
- ; CHECK-NEXT: %4.sub10:vreg_512_align2 = V_MOV_B32_e32 126, implicit $exec
- ; CHECK-NEXT: %4.sub11:vreg_512_align2 = V_MOV_B32_e32 127, implicit $exec
- ; CHECK-NEXT: %4.sub12:vreg_512_align2 = V_MOV_B32_e32 128, implicit $exec
- ; CHECK-NEXT: %4.sub13:vreg_512_align2 = V_MOV_B32_e32 129, implicit $exec
- ; CHECK-NEXT: %4.sub14:vreg_512_align2 = V_MOV_B32_e32 130, implicit $exec
- ; CHECK-NEXT: %4.sub15:vreg_512_align2 = V_MOV_B32_e32 131, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec
- ; CHECK-NEXT: %5.sub2:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec
- ; CHECK-NEXT: %5.sub3:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec
- ; CHECK-NEXT: %5.sub4:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec
- ; CHECK-NEXT: %5.sub5:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec
- ; CHECK-NEXT: %5.sub6:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec
- ; CHECK-NEXT: %5.sub7:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec
- ; CHECK-NEXT: %5.sub8:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec
- ; CHECK-NEXT: %5.sub9:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec
- ; CHECK-NEXT: %5.sub10:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec
- ; CHECK-NEXT: %5.sub11:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec
- ; CHECK-NEXT: %5.sub12:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec
- ; CHECK-NEXT: %5.sub13:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
- ; CHECK-NEXT: %5.sub14:vreg_512_align2 = V_MOV_B32_e32 216, implicit $exec
- ; CHECK-NEXT: %5.sub15:vreg_512_align2 = V_MOV_B32_e32 217, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_512_align2 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_512_align2 = V_MOV_B32_e32 3, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_512_align2 = V_MOV_B32_e32 4, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_512_align2 = V_MOV_B32_e32 5, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_512_align2 = V_MOV_B32_e32 6, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_512_align2 = V_MOV_B32_e32 7, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub8:vreg_512_align2 = V_MOV_B32_e32 8, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub9:vreg_512_align2 = V_MOV_B32_e32 9, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub10:vreg_512_align2 = V_MOV_B32_e32 10, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub11:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub12:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub13:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub14:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 116, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 117, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_512_align2 = V_MOV_B32_e32 118, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_512_align2 = V_MOV_B32_e32 119, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_512_align2 = V_MOV_B32_e32 120, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_512_align2 = V_MOV_B32_e32 121, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_512_align2 = V_MOV_B32_e32 122, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_512_align2 = V_MOV_B32_e32 123, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub8:vreg_512_align2 = V_MOV_B32_e32 124, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub9:vreg_512_align2 = V_MOV_B32_e32 125, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub10:vreg_512_align2 = V_MOV_B32_e32 126, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub11:vreg_512_align2 = V_MOV_B32_e32 127, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub12:vreg_512_align2 = V_MOV_B32_e32 128, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub13:vreg_512_align2 = V_MOV_B32_e32 129, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub14:vreg_512_align2 = V_MOV_B32_e32 130, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 131, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub8:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub9:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub10:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub11:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub12:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub13:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub14:vreg_512_align2 = V_MOV_B32_e32 216, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 217, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
%0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
@@ -4316,14 +4316,14 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_composition_sgpr_1024
- ; CHECK: undef %2.sub0:sgpr_288 = S_MOV_B32 34
- ; CHECK-NEXT: %2.sub4:sgpr_288 = S_MOV_B32 38
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub0_sub1_sub2_sub3_sub4
- ; CHECK-NEXT: S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8
- ; CHECK-NEXT: undef %3.sub0:sgpr_320 = S_MOV_B32 44
- ; CHECK-NEXT: %3.sub4:sgpr_320 = S_MOV_B32 48
- ; CHECK-NEXT: S_NOP 0, implicit %3.sub0_sub1_sub2_sub3_sub4_sub5
- ; CHECK-NEXT: S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8_sub9
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_288 = S_MOV_B32 34
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_288 = S_MOV_B32 38
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub0_sub1_sub2_sub3_sub4
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub4_sub5_sub6_sub7_sub8
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_320 = S_MOV_B32 44
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_320 = S_MOV_B32 48
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]].sub0_sub1_sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]].sub4_sub5_sub6_sub7_sub8_sub9
undef %3.sub4:sgpr_1024 = S_MOV_B32 34
%3.sub8:sgpr_1024 = S_MOV_B32 38
S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8
@@ -4403,12 +4403,12 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_128_w64
- ; CHECK: undef %2.sub0:sgpr_64 = S_MOV_B32 0
- ; CHECK-NEXT: %2.sub1:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:sgpr_64 = S_MOV_B32 12
- ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 13
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 12
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 13
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
undef %0.sub0:sgpr_128 = S_MOV_B32 00
%0.sub1:sgpr_128 = S_MOV_B32 01
S_NOP 0, implicit %0.sub0_sub1
@@ -4472,15 +4472,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_192_w64
- ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
- ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 24
- ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 25
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 12
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 13
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 24
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 25
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_192 = S_MOV_B32 00
%0.sub1:sgpr_192 = S_MOV_B32 01
S_NOP 0, implicit %0.sub0_sub1
@@ -4552,15 +4552,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_256_w64
- ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
- ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 26
- ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 27
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 12
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 13
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 26
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 27
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_256 = S_MOV_B32 00
%0.sub1:sgpr_256 = S_MOV_B32 01
S_NOP 0, implicit %0.sub0_sub1
@@ -4581,16 +4581,16 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_256_w128
- ; CHECK: undef %2.sub0:sgpr_128 = S_MOV_B32 0
- ; CHECK-NEXT: %2.sub1:sgpr_128 = S_MOV_B32 1
- ; CHECK-NEXT: %2.sub2:sgpr_128 = S_MOV_B32 2
- ; CHECK-NEXT: %2.sub3:sgpr_128 = S_MOV_B32 3
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:sgpr_128 = S_MOV_B32 14
- ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 15
- ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 16
- ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 17
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 3
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 14
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 15
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 16
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 17
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
undef %0.sub0:sgpr_256 = S_MOV_B32 00
%0.sub1:sgpr_256 = S_MOV_B32 01
%0.sub2:sgpr_256 = S_MOV_B32 02
@@ -4637,18 +4637,18 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_288_w160
- ; CHECK: undef %2.sub0:sgpr_160 = S_MOV_B32 0
- ; CHECK-NEXT: %2.sub1:sgpr_160 = S_MOV_B32 1
- ; CHECK-NEXT: %2.sub2:sgpr_160 = S_MOV_B32 2
- ; CHECK-NEXT: %2.sub3:sgpr_160 = S_MOV_B32 3
- ; CHECK-NEXT: %2.sub4:sgpr_160 = S_MOV_B32 4
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:sgpr_160 = S_MOV_B32 14
- ; CHECK-NEXT: %3.sub1:sgpr_160 = S_MOV_B32 15
- ; CHECK-NEXT: %3.sub2:sgpr_160 = S_MOV_B32 16
- ; CHECK-NEXT: %3.sub3:sgpr_160 = S_MOV_B32 17
- ; CHECK-NEXT: %3.sub4:sgpr_160 = S_MOV_B32 18
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_160 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_160 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_160 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_160 = S_MOV_B32 3
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_160 = S_MOV_B32 4
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_160 = S_MOV_B32 14
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_160 = S_MOV_B32 15
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_160 = S_MOV_B32 16
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_160 = S_MOV_B32 17
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_160 = S_MOV_B32 18
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
undef %0.sub0:sgpr_288 = S_MOV_B32 00
%0.sub1:sgpr_288 = S_MOV_B32 01
%0.sub2:sgpr_288 = S_MOV_B32 02
@@ -4694,15 +4694,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_320_w64
- ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
- ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 28
- ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 29
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 12
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 13
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 28
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 29
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_320 = S_MOV_B32 00
%0.sub1:sgpr_320 = S_MOV_B32 01
S_NOP 0, implicit %0.sub0_sub1
@@ -4725,20 +4725,20 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_320_w192
- ; CHECK: undef %2.sub0:sgpr_192 = S_MOV_B32 0
- ; CHECK-NEXT: %2.sub1:sgpr_192 = S_MOV_B32 1
- ; CHECK-NEXT: %2.sub2:sgpr_192 = S_MOV_B32 2
- ; CHECK-NEXT: %2.sub3:sgpr_192 = S_MOV_B32 3
- ; CHECK-NEXT: %2.sub4:sgpr_192 = S_MOV_B32 4
- ; CHECK-NEXT: %2.sub5:sgpr_192 = S_MOV_B32 5
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:sgpr_192 = S_MOV_B32 14
- ; CHECK-NEXT: %3.sub1:sgpr_192 = S_MOV_B32 15
- ; CHECK-NEXT: %3.sub2:sgpr_192 = S_MOV_B32 16
- ; CHECK-NEXT: %3.sub3:sgpr_192 = S_MOV_B32 17
- ; CHECK-NEXT: %3.sub4:sgpr_192 = S_MOV_B32 18
- ; CHECK-NEXT: %3.sub5:sgpr_192 = S_MOV_B32 19
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_192 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_192 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_192 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_192 = S_MOV_B32 3
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_192 = S_MOV_B32 4
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_192 = S_MOV_B32 5
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_192 = S_MOV_B32 14
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_192 = S_MOV_B32 15
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_192 = S_MOV_B32 16
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_192 = S_MOV_B32 17
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_192 = S_MOV_B32 18
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_192 = S_MOV_B32 19
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
undef %0.sub0:sgpr_320 = S_MOV_B32 00
%0.sub1:sgpr_320 = S_MOV_B32 01
%0.sub2:sgpr_320 = S_MOV_B32 02
@@ -4813,15 +4813,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_384_w64
- ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 110
- ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 111
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 22
- ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 23
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 110
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 111
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 22
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 23
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_384 = S_MOV_B32 00
%0.sub1:sgpr_384 = S_MOV_B32 01
S_NOP 0, implicit %0.sub0_sub1
@@ -4842,21 +4842,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_384_w128
- ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1
- ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2
- ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 14
- ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 15
- ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 16
- ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 17
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 28
- ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 29
- ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 210
- ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 211
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 3
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 14
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 15
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 16
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 17
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 28
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 29
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 210
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 211
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_384 = S_MOV_B32 00
%0.sub1:sgpr_384 = S_MOV_B32 01
%0.sub2:sgpr_384 = S_MOV_B32 02
@@ -4884,24 +4884,24 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_384_w256
- ; CHECK: undef %2.sub0:sgpr_256 = S_MOV_B32 0
- ; CHECK-NEXT: %2.sub1:sgpr_256 = S_MOV_B32 1
- ; CHECK-NEXT: %2.sub2:sgpr_256 = S_MOV_B32 2
- ; CHECK-NEXT: %2.sub3:sgpr_256 = S_MOV_B32 3
- ; CHECK-NEXT: %2.sub4:sgpr_256 = S_MOV_B32 4
- ; CHECK-NEXT: %2.sub5:sgpr_256 = S_MOV_B32 5
- ; CHECK-NEXT: %2.sub6:sgpr_256 = S_MOV_B32 6
- ; CHECK-NEXT: %2.sub7:sgpr_256 = S_MOV_B32 7
- ; CHECK-NEXT: S_NOP 0, implicit %2
- ; CHECK-NEXT: undef %3.sub0:sgpr_256 = S_MOV_B32 14
- ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 15
- ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 16
- ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 17
- ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 18
- ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 19
- ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 110
- ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 111
- ; CHECK-NEXT: S_NOP 0, implicit %3
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 3
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 4
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 5
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 6
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 7
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 14
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 15
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 16
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 17
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 18
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 19
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 110
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 111
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
undef %0.sub0:sgpr_384 = S_MOV_B32 00
%0.sub1:sgpr_384 = S_MOV_B32 01
%0.sub2:sgpr_384 = S_MOV_B32 02
@@ -4951,15 +4951,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_512_w64
- ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 114
- ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 115
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 22
- ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 23
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 114
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 115
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 22
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 23
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_512 = S_MOV_B32 00
%0.sub1:sgpr_512 = S_MOV_B32 01
S_NOP 0, implicit %0.sub0_sub1
@@ -4980,21 +4980,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_512_w128
- ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1
- ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2
- ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 112
- ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 113
- ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 114
- ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 115
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 24
- ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 25
- ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 26
- ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 27
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 3
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 112
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 113
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 114
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 115
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 24
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 25
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 26
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 27
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_512 = S_MOV_B32 00
%0.sub1:sgpr_512 = S_MOV_B32 01
%0.sub2:sgpr_512 = S_MOV_B32 02
@@ -5022,33 +5022,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_512_w256
- ; CHECK: undef %3.sub0:sgpr_256 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 1
- ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 2
- ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 3
- ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 4
- ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 5
- ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 6
- ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 7
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_256 = S_MOV_B32 14
- ; CHECK-NEXT: %4.sub1:sgpr_256 = S_MOV_B32 15
- ; CHECK-NEXT: %4.sub2:sgpr_256 = S_MOV_B32 16
- ; CHECK-NEXT: %4.sub3:sgpr_256 = S_MOV_B32 17
- ; CHECK-NEXT: %4.sub4:sgpr_256 = S_MOV_B32 18
- ; CHECK-NEXT: %4.sub5:sgpr_256 = S_MOV_B32 19
- ; CHECK-NEXT: %4.sub6:sgpr_256 = S_MOV_B32 110
- ; CHECK-NEXT: %4.sub7:sgpr_256 = S_MOV_B32 111
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_256 = S_MOV_B32 28
- ; CHECK-NEXT: %5.sub1:sgpr_256 = S_MOV_B32 29
- ; CHECK-NEXT: %5.sub2:sgpr_256 = S_MOV_B32 210
- ; CHECK-NEXT: %5.sub3:sgpr_256 = S_MOV_B32 211
- ; CHECK-NEXT: %5.sub4:sgpr_256 = S_MOV_B32 212
- ; CHECK-NEXT: %5.sub5:sgpr_256 = S_MOV_B32 213
- ; CHECK-NEXT: %5.sub6:sgpr_256 = S_MOV_B32 214
- ; CHECK-NEXT: %5.sub7:sgpr_256 = S_MOV_B32 215
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 3
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 4
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 5
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 6
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 7
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 14
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 15
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 16
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 17
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 18
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 19
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 110
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 111
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 28
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 29
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 210
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 211
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 212
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 213
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 214
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 215
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_512 = S_MOV_B32 00
%0.sub1:sgpr_512 = S_MOV_B32 01
%0.sub2:sgpr_512 = S_MOV_B32 02
@@ -5108,15 +5108,15 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_1024_w64
- ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
- ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 230
- ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 231
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 12
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 13
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 230
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 231
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_1024 = S_MOV_B32 00
%0.sub1:sgpr_1024 = S_MOV_B32 01
S_NOP 0, implicit %0.sub0_sub1
@@ -5137,21 +5137,21 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_1024_w128
- ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1
- ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2
- ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 128
- ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 129
- ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 130
- ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 131
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 24
- ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 25
- ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 26
- ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 27
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 3
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 128
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 129
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 130
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 131
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 24
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 25
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 26
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 27
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_1024 = S_MOV_B32 00
%0.sub1:sgpr_1024 = S_MOV_B32 01
%0.sub2:sgpr_1024 = S_MOV_B32 02
@@ -5179,33 +5179,33 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_1024_w256
- ; CHECK: undef %3.sub0:sgpr_256 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 1
- ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 2
- ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 3
- ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 4
- ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 5
- ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 6
- ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 7
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_256 = S_MOV_B32 124
- ; CHECK-NEXT: %4.sub1:sgpr_256 = S_MOV_B32 125
- ; CHECK-NEXT: %4.sub2:sgpr_256 = S_MOV_B32 126
- ; CHECK-NEXT: %4.sub3:sgpr_256 = S_MOV_B32 127
- ; CHECK-NEXT: %4.sub4:sgpr_256 = S_MOV_B32 128
- ; CHECK-NEXT: %4.sub5:sgpr_256 = S_MOV_B32 129
- ; CHECK-NEXT: %4.sub6:sgpr_256 = S_MOV_B32 130
- ; CHECK-NEXT: %4.sub7:sgpr_256 = S_MOV_B32 131
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_256 = S_MOV_B32 24
- ; CHECK-NEXT: %5.sub1:sgpr_256 = S_MOV_B32 25
- ; CHECK-NEXT: %5.sub2:sgpr_256 = S_MOV_B32 26
- ; CHECK-NEXT: %5.sub3:sgpr_256 = S_MOV_B32 27
- ; CHECK-NEXT: %5.sub4:sgpr_256 = S_MOV_B32 28
- ; CHECK-NEXT: %5.sub5:sgpr_256 = S_MOV_B32 29
- ; CHECK-NEXT: %5.sub6:sgpr_256 = S_MOV_B32 210
- ; CHECK-NEXT: %5.sub7:sgpr_256 = S_MOV_B32 211
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 3
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 4
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 5
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 6
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 7
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 124
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 125
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 126
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 127
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 128
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 129
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 130
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 131
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 24
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 25
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 26
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 27
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 28
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 29
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 210
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 211
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_1024 = S_MOV_B32 00
%0.sub1:sgpr_1024 = S_MOV_B32 01
%0.sub2:sgpr_1024 = S_MOV_B32 02
@@ -5243,57 +5243,57 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_1024_w512
- ; CHECK: undef %3.sub0:sgpr_512 = S_MOV_B32 0
- ; CHECK-NEXT: %3.sub1:sgpr_512 = S_MOV_B32 1
- ; CHECK-NEXT: %3.sub2:sgpr_512 = S_MOV_B32 2
- ; CHECK-NEXT: %3.sub3:sgpr_512 = S_MOV_B32 3
- ; CHECK-NEXT: %3.sub4:sgpr_512 = S_MOV_B32 4
- ; CHECK-NEXT: %3.sub5:sgpr_512 = S_MOV_B32 5
- ; CHECK-NEXT: %3.sub6:sgpr_512 = S_MOV_B32 6
- ; CHECK-NEXT: %3.sub7:sgpr_512 = S_MOV_B32 7
- ; CHECK-NEXT: %3.sub8:sgpr_512 = S_MOV_B32 8
- ; CHECK-NEXT: %3.sub9:sgpr_512 = S_MOV_B32 9
- ; CHECK-NEXT: %3.sub10:sgpr_512 = S_MOV_B32 10
- ; CHECK-NEXT: %3.sub11:sgpr_512 = S_MOV_B32 11
- ; CHECK-NEXT: %3.sub12:sgpr_512 = S_MOV_B32 12
- ; CHECK-NEXT: %3.sub13:sgpr_512 = S_MOV_B32 13
- ; CHECK-NEXT: %3.sub14:sgpr_512 = S_MOV_B32 14
- ; CHECK-NEXT: %3.sub15:sgpr_512 = S_MOV_B32 15
- ; CHECK-NEXT: S_NOP 0, implicit %3
- ; CHECK-NEXT: undef %4.sub0:sgpr_512 = S_MOV_B32 116
- ; CHECK-NEXT: %4.sub1:sgpr_512 = S_MOV_B32 117
- ; CHECK-NEXT: %4.sub2:sgpr_512 = S_MOV_B32 118
- ; CHECK-NEXT: %4.sub3:sgpr_512 = S_MOV_B32 119
- ; CHECK-NEXT: %4.sub4:sgpr_512 = S_MOV_B32 120
- ; CHECK-NEXT: %4.sub5:sgpr_512 = S_MOV_B32 121
- ; CHECK-NEXT: %4.sub6:sgpr_512 = S_MOV_B32 122
- ; CHECK-NEXT: %4.sub7:sgpr_512 = S_MOV_B32 123
- ; CHECK-NEXT: %4.sub8:sgpr_512 = S_MOV_B32 124
- ; CHECK-NEXT: %4.sub9:sgpr_512 = S_MOV_B32 125
- ; CHECK-NEXT: %4.sub10:sgpr_512 = S_MOV_B32 126
- ; CHECK-NEXT: %4.sub11:sgpr_512 = S_MOV_B32 127
- ; CHECK-NEXT: %4.sub12:sgpr_512 = S_MOV_B32 128
- ; CHECK-NEXT: %4.sub13:sgpr_512 = S_MOV_B32 129
- ; CHECK-NEXT: %4.sub14:sgpr_512 = S_MOV_B32 130
- ; CHECK-NEXT: %4.sub15:sgpr_512 = S_MOV_B32 131
- ; CHECK-NEXT: S_NOP 0, implicit %4
- ; CHECK-NEXT: undef %5.sub0:sgpr_512 = S_MOV_B32 24
- ; CHECK-NEXT: %5.sub1:sgpr_512 = S_MOV_B32 25
- ; CHECK-NEXT: %5.sub2:sgpr_512 = S_MOV_B32 26
- ; CHECK-NEXT: %5.sub3:sgpr_512 = S_MOV_B32 27
- ; CHECK-NEXT: %5.sub4:sgpr_512 = S_MOV_B32 28
- ; CHECK-NEXT: %5.sub5:sgpr_512 = S_MOV_B32 29
- ; CHECK-NEXT: %5.sub6:sgpr_512 = S_MOV_B32 210
- ; CHECK-NEXT: %5.sub7:sgpr_512 = S_MOV_B32 211
- ; CHECK-NEXT: %5.sub8:sgpr_512 = S_MOV_B32 212
- ; CHECK-NEXT: %5.sub9:sgpr_512 = S_MOV_B32 213
- ; CHECK-NEXT: %5.sub10:sgpr_512 = S_MOV_B32 214
- ; CHECK-NEXT: %5.sub11:sgpr_512 = S_MOV_B32 215
- ; CHECK-NEXT: %5.sub12:sgpr_512 = S_MOV_B32 216
- ; CHECK-NEXT: %5.sub13:sgpr_512 = S_MOV_B32 217
- ; CHECK-NEXT: %5.sub14:sgpr_512 = S_MOV_B32 218
- ; CHECK-NEXT: %5.sub15:sgpr_512 = S_MOV_B32 219
- ; CHECK-NEXT: S_NOP 0, implicit %5
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_512 = S_MOV_B32 0
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_512 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_512 = S_MOV_B32 2
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_512 = S_MOV_B32 3
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_512 = S_MOV_B32 4
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_512 = S_MOV_B32 5
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_512 = S_MOV_B32 6
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_512 = S_MOV_B32 7
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub8:sgpr_512 = S_MOV_B32 8
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub9:sgpr_512 = S_MOV_B32 9
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub10:sgpr_512 = S_MOV_B32 10
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub11:sgpr_512 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub12:sgpr_512 = S_MOV_B32 12
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub13:sgpr_512 = S_MOV_B32 13
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub14:sgpr_512 = S_MOV_B32 14
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub15:sgpr_512 = S_MOV_B32 15
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_512 = S_MOV_B32 116
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_512 = S_MOV_B32 117
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_512 = S_MOV_B32 118
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_512 = S_MOV_B32 119
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_512 = S_MOV_B32 120
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_512 = S_MOV_B32 121
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_512 = S_MOV_B32 122
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_512 = S_MOV_B32 123
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub8:sgpr_512 = S_MOV_B32 124
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub9:sgpr_512 = S_MOV_B32 125
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub10:sgpr_512 = S_MOV_B32 126
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub11:sgpr_512 = S_MOV_B32 127
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub12:sgpr_512 = S_MOV_B32 128
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub13:sgpr_512 = S_MOV_B32 129
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub14:sgpr_512 = S_MOV_B32 130
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub15:sgpr_512 = S_MOV_B32 131
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
+ ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_512 = S_MOV_B32 24
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_512 = S_MOV_B32 25
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_512 = S_MOV_B32 26
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_512 = S_MOV_B32 27
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub4:sgpr_512 = S_MOV_B32 28
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub5:sgpr_512 = S_MOV_B32 29
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub6:sgpr_512 = S_MOV_B32 210
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub7:sgpr_512 = S_MOV_B32 211
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub8:sgpr_512 = S_MOV_B32 212
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub9:sgpr_512 = S_MOV_B32 213
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub10:sgpr_512 = S_MOV_B32 214
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub11:sgpr_512 = S_MOV_B32 215
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub12:sgpr_512 = S_MOV_B32 216
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub13:sgpr_512 = S_MOV_B32 217
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub14:sgpr_512 = S_MOV_B32 218
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub15:sgpr_512 = S_MOV_B32 219
+ ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_1024 = S_MOV_B32 00
%0.sub1:sgpr_1024 = S_MOV_B32 01
%0.sub2:sgpr_1024 = S_MOV_B32 02
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
index 135d8b8e8ae9796..58753081198cf58 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
@@ -7,26 +7,26 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_composition_vreg_1024
- ; CHECK: undef %5.sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
- ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1
- ; CHECK-NEXT: S_NOP 0, implicit %5.sub1_sub2
- ; CHECK-NEXT: undef %6.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
- ; CHECK-NEXT: %6.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2
- ; CHECK-NEXT: S_NOP 0, implicit %6.sub1_sub2_sub3
- ; CHECK-NEXT: undef %7.sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
- ; CHECK-NEXT: %7.sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3
- ; CHECK-NEXT: S_NOP 0, implicit %7.sub1_sub2_sub3_sub4
- ; CHECK-NEXT: undef %8.sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
- ; CHECK-NEXT: %8.sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %8.sub0_sub1_sub2_sub3_sub4
- ; CHECK-NEXT: S_NOP 0, implicit %8.sub1_sub2_sub3_sub4_sub5
- ; CHECK-NEXT: undef %9.sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
- ; CHECK-NEXT: %9.sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
- ; CHECK-NEXT: S_NOP 0, implicit %9.sub0_sub1_sub2_sub3_sub4_sub5
- ; CHECK-NEXT: S_NOP 0, implicit %9.sub2_sub3_sub4_sub5_sub6_sub7
+ ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0_sub1
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1_sub2
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub0_sub1_sub2
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1_sub2_sub3
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub0_sub1_sub2_sub3
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub1_sub2_sub3_sub4
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_3:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub0_sub1_sub2_sub3_sub4
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub1_sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: undef [[V_MOV_B32_e32_4:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub0_sub1_sub2_sub3_sub4_sub5
+ ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub2_sub3_sub4_sub5_sub6_sub7
undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
S_NOP 0, implicit %0.sub1_sub2
@@ -58,9 +58,9 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions
- ; CHECK: undef %2.sub0:sgpr_64 = S_MOV_B32 1
- ; CHECK-NEXT: %2.sub1:sgpr_64 = S_MOV_B32 2
- ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY %2
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 2
+ ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B32_]]
undef %0.sub4:sgpr_1024 = S_MOV_B32 01
%0.sub5:sgpr_1024 = S_MOV_B32 02
%1:vreg_64 = COPY %0.sub4_sub5
>From 447b05a7829e163d23585bf76d10a82ad46e0e5a Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: Mon, 23 Oct 2023 17:49:51 +0200
Subject: [PATCH 2/5] add test to illustrate the problem
---
.../test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
index 58753081198cf58..01ebacfecf8121d 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs %s -o /dev/null 2>&1
---
name: test_subregs_composition_vreg_1024
tracksRegLiveness: true
@@ -87,4 +86,15 @@ body: |
undef %0.sub2_sub3:sgpr_128 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
%2:vreg_64 = COPY %0.sub2_sub3:sgpr_128
...
+---
+name: test_vgpr_selected_instead_of_sgpr_because_use_allows_both
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_vgpr_selected_instead_of_sgpr_because_use_allows_both
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY undef %1:sgpr_32
+ ; CHECK-NEXT: dead [[V_LSHL_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_ADD_U32_e64 [[COPY]], 2, undef %3:vgpr_32, implicit $exec
+ undef %1.sub1:sgpr_96 = COPY undef %0:sgpr_32
+ %3:vgpr_32 = V_LSHL_ADD_U32_e64 %1.sub1:sgpr_96, 2, undef %2:vgpr_32, implicit $exec
+...
>From 2d6fc2ddb4a798e91ad3a2375319a8eab012c7f5 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: Mon, 23 Oct 2023 17:56:51 +0200
Subject: [PATCH 3/5] fix by taking original subreg regclass into account.
---
.../AMDGPU/GCNRewritePartialRegUses.cpp | 59 +++++++-------
.../AMDGPU/rewrite-partial-reg-uses-gen.mir | 76 +++++++++----------
.../AMDGPU/rewrite-partial-reg-uses.mir | 4 +-
3 files changed, 70 insertions(+), 69 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
index 99db7e4af9fd1c9..c94e5c16fb2cf2e 100644
--- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
@@ -101,17 +101,16 @@ class GCNRewritePartialRegUses : public MachineFunctionPass {
/// find new regclass such that:
/// 1. It has subregs obtained by shifting each OldSubReg by RShift number
/// of bits to the right. Every "shifted" subreg should have the same
- /// SubRegRC. SubRegRC can be null, in this case it initialized using
- /// getSubRegisterClass. If CoverSubregIdx is not zero it's a subreg that
- /// "covers" all other subregs in pairs. Basically such subreg becomes a
- /// whole register.
+ /// SubRegRC. If CoverSubregIdx is not zero it's a subreg that "covers"
+ /// all other subregs in pairs. Basically such subreg becomes a whole
+ /// register.
/// 2. Resulting register class contains registers of minimal size but not
/// less than RegNumBits.
///
/// SubRegs is map of OldSubReg -> [SubRegRC, NewSubReg] and is used as in/out
/// parameter:
/// OldSubReg - input parameter,
- /// SubRegRC - in/out, should be changed for unknown regclass,
+ /// SubRegRC - input parameter (cannot be null),
/// NewSubReg - output, contains shifted subregs on return.
const TargetRegisterClass *
getRegClassWithShiftedSubregs(const TargetRegisterClass *RC, unsigned RShift,
@@ -228,19 +227,7 @@ GCNRewritePartialRegUses::getRegClassWithShiftedSubregs(
BitVector ClassMask(getAllocatableAndAlignedRegClassMask(RCAlign));
for (auto &[OldSubReg, SRI] : SubRegs) {
auto &[SubRegRC, NewSubReg] = SRI;
-
- // Register class may be unknown, for example:
- // undef %0.sub4:sgpr_1024 = S_MOV_B32 01
- // %0.sub5:sgpr_1024 = S_MOV_B32 02
- // %1:vreg_64 = COPY %0.sub4_sub5
- // Register classes for subregs 'sub4' and 'sub5' are known from the
- // description of destination operand of S_MOV_B32 instruction but the
- // class for the subreg 'sub4_sub5' isn't specified by the COPY instruction.
- if (!SubRegRC)
- SubRegRC = TRI->getSubRegisterClass(RC, OldSubReg);
-
- if (!SubRegRC)
- return nullptr;
+ assert(SubRegRC);
LLVM_DEBUG(dbgs() << " " << TRI->getSubRegIndexName(OldSubReg) << ':'
<< TRI->getRegClassName(SubRegRC)
@@ -248,6 +235,8 @@ GCNRewritePartialRegUses::getRegClassWithShiftedSubregs(
<< " -> ");
if (OldSubReg == CoverSubregIdx) {
+ // Covering subreg will become a full register, RC should be allocatable.
+ assert(SubRegRC->isAllocatable());
NewSubReg = AMDGPU::NoSubRegister;
LLVM_DEBUG(dbgs() << "whole reg");
} else {
@@ -425,7 +414,7 @@ bool GCNRewritePartialRegUses::rewriteReg(Register Reg) const {
return false;
for (MachineOperand &MO : Range) {
- if (MO.getSubReg() == AMDGPU::NoSubRegister) // Whole reg used, quit.
+ if (MO.getSubReg() == AMDGPU::NoSubRegister) // Whole reg used, quit. [1]
return false;
}
@@ -433,21 +422,33 @@ bool GCNRewritePartialRegUses::rewriteReg(Register Reg) const {
LLVM_DEBUG(dbgs() << "Try to rewrite partial reg " << printReg(Reg, TRI)
<< ':' << TRI->getRegClassName(RC) << '\n');
- // Collect used subregs and constrained reg classes infered from instruction
+ // Collect used subregs and their reg classes infered from instruction
// operands.
SubRegMap SubRegs;
for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
- assert(MO.getSubReg() != AMDGPU::NoSubRegister);
- auto *OpDescRC = getOperandRegClass(MO);
- const auto [I, Inserted] = SubRegs.try_emplace(MO.getSubReg(), OpDescRC);
- if (!Inserted && OpDescRC) {
- SubRegInfo &SRI = I->second;
- SRI.RC = SRI.RC ? TRI->getCommonSubClass(SRI.RC, OpDescRC) : OpDescRC;
- if (!SRI.RC) {
- LLVM_DEBUG(dbgs() << " Couldn't find common target regclass\n");
- return false;
+ const unsigned SubReg = MO.getSubReg();
+ assert(SubReg != AMDGPU::NoSubRegister); // Due to [1].
+ LLVM_DEBUG(dbgs() << " " << TRI->getSubRegIndexName(SubReg) << ':');
+
+ const auto [I, Inserted] = SubRegs.try_emplace(SubReg);
+ const TargetRegisterClass *&SubRegRC = I->second.RC;
+
+ if (Inserted)
+ SubRegRC = TRI->getSubRegisterClass(RC, SubReg);
+
+ if (SubRegRC) {
+ if (const TargetRegisterClass *OpDescRC = getOperandRegClass(MO)) {
+ LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << " & "
+ << TRI->getRegClassName(OpDescRC) << " = ");
+ SubRegRC = TRI->getCommonSubClass(SubRegRC, OpDescRC);
}
}
+
+ if (!SubRegRC) {
+ LLVM_DEBUG(dbgs() << "couldn't find target regclass\n");
+ return false;
+ } else
+ LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << '\n');
}
auto *NewRC = getMinSizeReg(RC, SubRegs);
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
index 86434d1f71a5a88..037f39df8c3e06e 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
@@ -4341,9 +4341,9 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_64_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
undef %0.sub0:sgpr_64 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4358,11 +4358,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_96_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 22
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 22
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_96 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4381,11 +4381,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_128_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 23
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 23
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_128 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4425,11 +4425,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_160_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 24
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 24
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_160 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4450,11 +4450,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_192_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 25
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 25
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_192 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4503,11 +4503,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_224_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 26
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 26
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_224 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4530,11 +4530,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_256_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 27
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 27
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_256 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4612,11 +4612,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_288_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 28
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 28
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_288 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4672,11 +4672,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_320_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 29
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 29
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_320 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4763,11 +4763,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_352_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 210
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 210
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_352 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4791,11 +4791,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_384_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 211
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 211
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_384 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -4929,11 +4929,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_512_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 215
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 215
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_512 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
@@ -5086,11 +5086,11 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_sgpr_1024_w32
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
- ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 231
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 231
; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
undef %0.sub0:sgpr_1024 = S_MOV_B32 00
S_NOP 0, implicit %0.sub0
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
index 01ebacfecf8121d..07e49dcdafd8cc3 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
@@ -81,7 +81,7 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
- ; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
+ ; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sgpr_64 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
undef %0.sub2_sub3:sgpr_128 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
%2:vreg_64 = COPY %0.sub2_sub3:sgpr_128
@@ -92,7 +92,7 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_vgpr_selected_instead_of_sgpr_because_use_allows_both
- ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY undef %1:sgpr_32
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = COPY undef %1:sgpr_32
; CHECK-NEXT: dead [[V_LSHL_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_ADD_U32_e64 [[COPY]], 2, undef %3:vgpr_32, implicit $exec
undef %1.sub1:sgpr_96 = COPY undef %0:sgpr_32
%3:vgpr_32 = V_LSHL_ADD_U32_e64 %1.sub1:sgpr_96, 2, undef %2:vgpr_32, implicit $exec
>From c7270e0818c54a89cb3b4d93eaac08ec5347a997 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: Tue, 24 Oct 2023 08:04:10 +0200
Subject: [PATCH 4/5] comments
---
llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
index c94e5c16fb2cf2e..f5993c0a0d9eef3 100644
--- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
@@ -447,8 +447,8 @@ bool GCNRewritePartialRegUses::rewriteReg(Register Reg) const {
if (!SubRegRC) {
LLVM_DEBUG(dbgs() << "couldn't find target regclass\n");
return false;
- } else
- LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << '\n');
+ }
+ LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << '\n');
}
auto *NewRC = getMinSizeReg(RC, SubRegs);
>From e62a4d1afa5552abcaa2b8a58e424820de648885 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: Wed, 15 Nov 2023 19:10:08 +0100
Subject: [PATCH 5/5] comments
---
llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
index f5993c0a0d9eef3..019b64dd871e2a7 100644
--- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
@@ -410,14 +410,11 @@ GCNRewritePartialRegUses::getOperandRegClass(MachineOperand &MO) const {
bool GCNRewritePartialRegUses::rewriteReg(Register Reg) const {
auto Range = MRI->reg_nodbg_operands(Reg);
- if (Range.begin() == Range.end())
+ if (Range.empty() || any_of(Range, [](MachineOperand &MO) {
+ return MO.getSubReg() == AMDGPU::NoSubRegister; // Whole reg used. [1]
+ }))
return false;
- for (MachineOperand &MO : Range) {
- if (MO.getSubReg() == AMDGPU::NoSubRegister) // Whole reg used, quit. [1]
- return false;
- }
-
auto *RC = MRI->getRegClass(Reg);
LLVM_DEBUG(dbgs() << "Try to rewrite partial reg " << printReg(Reg, TRI)
<< ':' << TRI->getRegClassName(RC) << '\n');
@@ -425,7 +422,7 @@ bool GCNRewritePartialRegUses::rewriteReg(Register Reg) const {
// Collect used subregs and their reg classes infered from instruction
// operands.
SubRegMap SubRegs;
- for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
+ for (MachineOperand &MO : Range) {
const unsigned SubReg = MO.getSubReg();
assert(SubReg != AMDGPU::NoSubRegister); // Due to [1].
LLVM_DEBUG(dbgs() << " " << TRI->getSubRegIndexName(SubReg) << ':');
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