[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[Liao Chunyu via Phabricator via cfe-commits]

liaolucy updated this revision to Diff 558107.
liaolucy added a comment.

1. use a custom parser to parse Register-Register load/store
2. Rebase

Thanks


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158824/new/

https://reviews.llvm.org/D158824

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/corev/XCVelw-invalid.s
  llvm/test/MC/RISCV/corev/XCVelw-valid.s
  llvm/test/MC/RISCV/corev/XCVmem-invalid.s
  llvm/test/MC/RISCV/corev/XCVmem-valid.s
  llvm/unittests/Support/RISCVISAInfoTest.cpp

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