[llvm] [clang] [clang-tools-extra] [AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (PR #71710)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Nov 13 05:53:12 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-globalisel
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
This reverts commit 201f892b3b597f24287ab6a712a286e25a45a7d9.
---
Patch is 1.27 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/71710.diff
55 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll (+6-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll (+231-231)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll (+83-86)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll (+268-329)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll (+387-440)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll (+246-246)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll (+182-182)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll (+320-346)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll (+92-119)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (+925-975)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll (+290-296)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll (-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll (+99-125)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (+940-992)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+306-332)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll (+50-50)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll (+65-65)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll (+171-177)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll (+23-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll (+293-370)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll (+50-50)
- (modified) llvm/test/CodeGen/AMDGPU/clamp.ll (+8-7)
- (modified) llvm/test/CodeGen/AMDGPU/ds-alignment.ll (+23-24)
- (modified) llvm/test/CodeGen/AMDGPU/fma.f16.ll (+43-41)
- (modified) llvm/test/CodeGen/AMDGPU/fmed3.ll (+73-70)
- (modified) llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll (+30-14)
- (modified) llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll (+13-14)
- (modified) llvm/test/CodeGen/AMDGPU/fold-readlane.mir (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/fptoui.f16.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll (+409-377)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll (+2-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp.ll (+584-606)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.ll (+87-111)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.frexp.ll (+72-48)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll (+59-59)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+441-476)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+441-476)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+87-111)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+392-406)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i16.ll (+458-444)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix.ll (+87-57)
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll (+14-19)
- (modified) llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll (+6-6)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 45294da5df5916a..0ec0370e21dfc16 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -717,24 +717,6 @@ void SIFoldOperands::foldOperand(
const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg);
if (!DestReg.isPhysical()) {
- if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
- SmallVector<FoldCandidate, 4> CopyUses;
- for (auto &Use : MRI->use_nodbg_operands(DestReg)) {
- // There's no point trying to fold into an implicit operand.
- if (Use.isImplicit())
- continue;
-
- CopyUses.emplace_back(Use.getParent(),
- Use.getParent()->getOperandNo(&Use),
- &UseMI->getOperand(1));
- }
-
- for (auto &F : CopyUses) {
- foldOperand(*F.OpToFold, F.UseMI, F.UseOpNo, FoldList,
- CopiesToReplace);
- }
- }
-
if (DestRC == &AMDGPU::AGPR_32RegClass &&
TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64));
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
index 26d1fbb09210c64..e4cababfe1c919a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
@@ -165,9 +165,8 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
; GFX7-LABEL: v_add_v2i16_neg_inline_imm_splat:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0xffc0
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, s4, v0
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, s4, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc0, v0
+; GFX7-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_neg_inline_imm_splat:
@@ -180,10 +179,10 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
; GFX8-LABEL: v_add_v2i16_neg_inline_imm_splat:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffc0
-; GFX8-NEXT: v_add_u16_e32 v1, 0xffc0, v0
-; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffc0
+; GFX8-NEXT: v_add_u16_e32 v2, 0xffc0, v0
+; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_add_v2i16_neg_inline_imm_splat:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
index 9da75b093fc9cb5..1a8529b9101c3fb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
@@ -436,15 +436,15 @@ define float @v_fdiv_f32_ulp25(float %a, float %b) {
; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
+; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -569,15 +569,15 @@ define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
+; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -587,15 +587,15 @@ define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
+; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -1527,25 +1527,25 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v5, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
-; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v6, v0
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v5
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v5, v0, v5, vcc
+; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v6, v0, v6, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v3
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v5, v4
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v6, v4
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v4, v0
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v1
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
@@ -1557,19 +1557,19 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
; GCN-FLUSH: ; %bb.0:
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-FLUSH-NEXT: s_mov_b32 s4, 0x6f800000
-; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x2f800000
-; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, s4
-; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
-; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, s4
-; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc
-; GCN-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v5
+; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x6f800000
+; GCN-FLUSH-NEXT: v_mov_b32_e32 v5, 0x2f800000
+; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, v4
+; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc
+; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, v4
+; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v5, vcc
+; GCN-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v6
; GCN-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v4
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GCN-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3
-; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v5, v0
+; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v6, v0
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
@@ -2316,16 +2316,16 @@ define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) {
; GFX6-IEEE-LABEL: v_rcp_v2f32_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
@@ -2425,9 +2425,9 @@ define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v5, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v2
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v4
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
@@ -2435,7 +2435,7 @@ define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v2, v4, v2
; GFX6-IEEE-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v3
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v5
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
@@ -2863,15 +2863,15 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf(float %x, float %y, float %z)
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
+; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -2881,15 +2881,15 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf(float %x, float %y, float %z)
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v3, v0
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
+; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -2983,15 +2983,15 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user(float %x, fl
; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v1
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v4
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v3
-; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v0
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -3002,15 +3002,15 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user(float %x, fl
; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-FLUSH-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v3, v1
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v4
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
-; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v5, v0
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -3391,15 +3391,15 @@ define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX6-IEEE: ; %bb.0:
; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-IEEE-NEXT: v_frexp_mant_f32_e64 v3, -v0
-; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-IEEE-NEXT: v_frexp_mant_f32_e64 v4, -v0
+; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-IEEE-NEXT: v_cndmask_b32_e64 v3, -v0, v3, s[4:5]
+; GFX6-IEEE-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]
; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -3409,15 +3409,15 @@ define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX6-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
; GFX6-FLUSH: ; %bb.0:
; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
-; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e64 v3, -v0
-; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e64 v4, -v0
+; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v3
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT: v_cndmask_b32_e64 v3, -v0, v3, s[4:5]
+; GFX6-FLUSH-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]
; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e64 v0, -v0
; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -3820,121 +3820,121 @@ define float @v_fdiv_f32_constrhs0_dynamic(float %x) #0 {
; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
; GFX6-IEEE-FASTFMA: ; %bb.0:
; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
-; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
-; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
-; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e400
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
-; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
-; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
-; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
-; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
-; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4
-; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
-; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-IEEE-FASTFMA-N...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/71710
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