[llvm] [clang] [AArch64] Add quadword gather load/scatter store intrinsics with unscaled vector offset (PR #71290)

[Momchil Velikov via cfe-commits]

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@@ -9497,8 +9500,11 @@ Value *CodeGenFunction::EmitSVEScatterStore(const SVETypeFlags &TypeFlags,
   // mapped to <n x 16 x i1>. However, this might be incompatible with the
   // actual type being stored. For example, when storing doubles (i64) the
   // predicated should be <n x 2 x i1> instead. At the IR level the type of
-  // the predicate and the data being stored must match. Cast accordingly.
-  Ops[1] = EmitSVEPredicateCast(Ops[1], OverloadedTy);
+  // the predicate and the data being stored must match. Cast to the type
+  // expected by the intrinsic. The intrinsic itself should be defined in
+  // a way that enforces relations between parameter types.
+  Ops[1] = EmitSVEPredicateCast(
+      Ops[1], cast<llvm::ScalableVectorType>(F->getArg(1)->getType()));
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momchil-velikov wrote:

The elaborate a bit, that's the point of rotating the last argument to the front - to make the arguments match the parameters, cf. https://github.com/momchil-velikov/llvm-project/blob/18bb9725619569687bec2c013768511105266a5e/clang/lib/CodeGen/CGBuiltin.cpp#L9448

In the store intrinsics, the first parameter (`F->getArg(0)`) is the value to store, the second parameter (`F->getArg(1)`) is the predicate.

https://github.com/llvm/llvm-project/pull/71290