[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

[Kerry McLaughlin via cfe-commits]

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@@ -296,5 +296,28 @@ multiclass ZAAddSub<string n_suffix> {
   }
 }
 
+////////////////////////////////////////////////////////////////////////////////
+// SME2 - MIN, MAX
+
+multiclass MinMaxIntr<string i, string zm, string mul, string t> {
+  def SVS # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "csil",     MergeNone, "aarch64_sve_s" # i # zm # "_" # mul, [IsStreaming], []>;
+  def SVU # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "UcUsUiUl", MergeNone, "aarch64_sve_u" # i # zm # "_" # mul, [IsStreaming], []>;
+  def SVF # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "hfd",      MergeNone, "aarch64_sve_f" # i # zm # "_" # mul, [IsStreaming], []>;
+}
+
+let TargetGuard = "sme2" in {
+  // SMAX / UMAX / FMAX
+  defm MAX_SINGLE_X2 : MinMaxIntr<"max", "_single", "x2", "22d">;
+  defm MAX_MULTI_X2  : MinMaxIntr<"max", "",        "x2", "222">;
+  defm MAX_SINGLE_X4 : MinMaxIntr<"max", "_single", "x4", "44d">;
+  defm MAX_MULTI_X4  : MinMaxIntr<"max", "",        "x4", "444">;
+
+  // SMIN / UMIN / FMIN
+  defm MIN_SINGLE_X2 : MinMaxIntr<"min", "_single", "x2", "22d">;
+  defm MIN_MULTI_X2  : MinMaxIntr<"min", "",        "x2", "222">;
+  defm MIN_SINGLE_X4 : MinMaxIntr<"min", "_single", "x4", "44d">;
+  defm MIN_MULTI_X4  : MinMaxIntr<"min", "",        "x4", "444">;
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kmclaughlin-arm wrote:

Hi Sam, please can you add the definitions for any builtins that operate on vectors only (and not ZA) to arm_sve.td? The reason for this is that these builtins could possibly become SVE instructions in the future. The LLVM IR intrinsic names will also begin with "aarch64_sve" for this reason.

https://github.com/llvm/llvm-project/pull/71688