[clang] [clang-format] Add space in Verilog tagged unions (PR #71354)

[Björn Schäpers via cfe-commits]

================
@@ -4694,8 +4694,15 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line,
         Left.isOneOf(TT_VerilogDimensionedTypeName, Keywords.kw_function)) {
       return true;
     }
+    // In a tagged union expression, there should be a space after the tag.
+    if (Right.isOneOf(tok::period, Keywords.kw_apostrophe) &&
+        Keywords.isVerilogIdentifier(Left) && Left.getPreviousNonComment() &&
+        Left.getPreviousNonComment()->is(Keywords.kw_tagged)) {
+      return true;
+    }
     // Don't add spaces between a casting type and the quote or repetition count
-    // and the brace.
+    // and the brace.  The case of tagged union expressions is handled by the
----------------
HazardyKnusperkeks wrote:

```suggestion
    // and the brace. The case of tagged union expressions is handled by the
```

https://github.com/llvm/llvm-project/pull/71354