[clang] [llvm] [PowerPC] Add an alias for -mregnames so that full register names used in assembly. (PR #70255)
Stefan Pintilie via cfe-commits
cfe-commits at lists.llvm.org
Fri Nov 3 20:39:10 PDT 2023
https://github.com/stefanp-ibm updated https://github.com/llvm/llvm-project/pull/70255
>From b09304032b13927bfa9e1920313ba1193cfd53ad Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 25 Oct 2023 15:21:11 -0500
Subject: [PATCH 1/7] [PowerPC] Add an alias for -mregnames so that full
register names used in assembly.
This option already exists on GCC and so it is being added to LLVM so that we
use the same option as them.
---
clang/include/clang/Driver/Options.td | 4 +
clang/lib/Basic/Targets/PPC.cpp | 6 ++
clang/lib/Basic/Targets/PPC.h | 1 +
.../test/CodeGen/PowerPC/ppc-full-reg-names.c | 78 +++++++++++++++++++
.../PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 15 ++--
.../PowerPC/MCTargetDesc/PPCInstPrinter.h | 5 +-
llvm/lib/Target/PowerPC/PPC.td | 4 +
.../CodeGen/PowerPC/ppc-full-reg-names.ll | 62 +++++++++++++++
8 files changed, 167 insertions(+), 8 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
create mode 100644 llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index fcf6a4b2ccb2369..339966a36b513bc 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4777,6 +4777,10 @@ def mrop_protect : Flag<["-"], "mrop-protect">,
Group<m_ppc_Features_Group>;
def mprivileged : Flag<["-"], "mprivileged">,
Group<m_ppc_Features_Group>;
+def mregnames : Flag<["-"], "mregnames">, Group<m_ppc_Features_Group>,
+ Visibility<[ClangOption]>;
+def mno_regnames : Flag<["-"], "mno-regnames">, Group<m_ppc_Features_Group>,
+ Visibility<[ClangOption]>;
} // let Flags = [TargetSpecific]
def maix_small_local_exec_tls : Flag<["-"], "maix-small-local-exec-tls">,
Group<m_ppc_Features_Group>,
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 5ce276e1af9ef64..211d9a0295c9ad9 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -89,6 +89,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
IsISA3_1 = true;
} else if (Feature == "+quadword-atomics") {
HasQuadwordAtomics = true;
+ } else if (Feature == "+regnames") {
+ FullRegisterNames = true;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@@ -551,6 +553,9 @@ bool PPCTargetInfo::initFeatureMap(
// off by default.
Features["aix-small-local-exec-tls"] = false;
+ // By default full register names are not used in assembly.
+ Features["regnames"] = false;
+
Features["spe"] = llvm::StringSwitch<bool>(CPU)
.Case("8548", true)
.Case("e500", true)
@@ -700,6 +705,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Case("isa-v30-instructions", IsISA3_0)
.Case("isa-v31-instructions", IsISA3_1)
.Case("quadword-atomics", HasQuadwordAtomics)
+ .Case("regnames", FullRegisterNames)
.Default(false);
}
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 4d62673ba7fb8c5..ddef057bb306cad 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
+ bool FullRegisterNames = false;
protected:
std::string ABI;
diff --git a/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
new file mode 100644
index 000000000000000..c1bd22c1134c9a7
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
@@ -0,0 +1,78 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
+// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
+
+// Also check the assembly to make sure that the full names are used.
+// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mregnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
+// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mno-regnames \
+// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
+
+
+
+// FULLNAMES-LABEL: @IntNames
+// FULLNAMES-SAME: #0
+// NOFULLNAMES-LABEL: @IntNames
+// NOFULLNAMES-SAME: #0
+// ASMFULLNAMES-LABEL: IntNames:
+// ASMFULLNAMES: add r3, r4, r3
+// ASMFULLNAMES: blr
+// ASMNOFULLNAMES-LABEL: IntNames:
+// ASMNOFULLNAMES: add 3, 4, 3
+// ASMNOFULLNAMES: blr
+int IntNames(int a, int b) {
+ return a + b;
+}
+
+// FULLNAMES-LABEL: @FPNames
+// FULLNAMES-SAME: #0
+// NOFULLNAMES-LABEL: @FPNames
+// NOFULLNAMES-SAME: #0
+// ASMFULLNAMES-LABEL: FPNames:
+// ASMFULLNAMES: xsadddp f1, f1, f2
+// ASMFULLNAMES: blr
+// ASMNOFULLNAMES-LABEL: FPNames:
+// ASMNOFULLNAMES: xsadddp 1, 1, 2
+// ASMNOFULLNAMES: blr
+double FPNames(double a, double b) {
+ return a + b;
+}
+
+// FULLNAMES-LABEL: @VecNames
+// FULLNAMES-SAME: #0
+// NOFULLNAMES-LABEL: @VecNames
+// NOFULLNAMES-SAME: #0
+// ASMFULLNAMES-LABEL: VecNames:
+// ASMFULLNAMES: xvaddsp vs34, vs34, vs35
+// ASMFULLNAMES: blr
+// ASMNOFULLNAMES-LABEL: VecNames:
+// ASMNOFULLNAMES: xvaddsp 34, 34, 35
+// ASMNOFULLNAMES: blr
+vector float VecNames(vector float a, vector float b) {
+ return a + b;
+}
+
+// FULLNAMES: attributes #0 = {
+// FULLNAMES-SAME: +regnames
+// NOFULLNAMES: attributes #0 = {
+// NOFULLNAMES-SAME: -regnames
+
+
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index 0ee7f9f49843172..17498627a84fdfd 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -614,9 +614,11 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
/// getVerboseConditionalRegName - This method expands the condition register
/// when requested explicitly or targetting Darwin.
const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
- unsigned RegEncoding)
+ unsigned RegEncoding,
+ const MCSubtargetInfo &STI)
const {
- if (!FullRegNames)
+ // __SP__
+ if (!FullRegNames && !STI.hasFeature(PPC::FeatureFullRegisterNames))
return nullptr;
if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
return nullptr;
@@ -635,8 +637,9 @@ const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
// showRegistersWithPrefix - This method determines whether registers
// should be number-only or include the prefix.
-bool PPCInstPrinter::showRegistersWithPrefix() const {
- return FullRegNamesWithPercent || FullRegNames;
+bool PPCInstPrinter::showRegistersWithPrefix(const MCSubtargetInfo &STI) const {
+ return FullRegNamesWithPercent || FullRegNames ||
+ STI.hasFeature(PPC::FeatureFullRegisterNames);
}
void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -648,12 +651,12 @@ void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo);
const char *RegName;
- RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
+ RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg), STI);
if (RegName == nullptr)
RegName = getRegisterName(Reg);
if (showRegistersWithPercentPrefix(RegName))
O << "%";
- if (!showRegistersWithPrefix())
+ if (!showRegistersWithPrefix(STI))
RegName = PPC::stripRegisterPrefix(RegName);
O << RegName;
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
index 6ba3eb4c79dc990..2e29971a20fc593 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
@@ -22,9 +22,10 @@ class PPCInstPrinter : public MCInstPrinter {
Triple TT;
private:
bool showRegistersWithPercentPrefix(const char *RegName) const;
- bool showRegistersWithPrefix() const;
+ bool showRegistersWithPrefix(const MCSubtargetInfo &STI) const;
const char *getVerboseConditionRegName(unsigned RegNum,
- unsigned RegEncoding) const;
+ unsigned RegEncoding,
+ const MCSubtargetInfo &STI) const;
public:
PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 535616d33a8032a..568a3d4b5a2aab1 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -338,6 +338,10 @@ def FeaturePredictableSelectIsExpensive :
def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
"MFLR is a fast instruction">;
+def FeatureFullRegisterNames :
+ SubtargetFeature<"regnames", "FullRegisterNames", "true",
+ "Use full register names in assembly.">;
+
// Since new processors generally contain a superset of features of those that
// came before them, the idea is to make implementations of new processors
// less error prone and easier to read.
diff --git a/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll b/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll
new file mode 100644
index 000000000000000..cb0dcaf7566bcdd
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll
@@ -0,0 +1,62 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
+; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu < %s \
+; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
+; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
+; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu < %s \
+; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
+; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s
+
+
+define dso_local signext i32 @IntNames(i32 noundef signext %a, i32 noundef signext %b) local_unnamed_addr #0 {
+; FULLNAMES-LABEL: IntNames:
+; FULLNAMES: # %bb.0: # %entry
+; FULLNAMES-NEXT: add r3, r4, r3
+; FULLNAMES-NEXT: extsw r3, r3
+; FULLNAMES-NEXT: blr
+;
+; NOFULLNAMES-LABEL: IntNames:
+; NOFULLNAMES: # %bb.0: # %entry
+; NOFULLNAMES-NEXT: add 3, 4, 3
+; NOFULLNAMES-NEXT: extsw 3, 3
+; NOFULLNAMES-NEXT: blr
+entry:
+ %add = add nsw i32 %b, %a
+ ret i32 %add
+}
+
+define dso_local double @FPNames(double noundef %a, double noundef %b) local_unnamed_addr #0 {
+; FULLNAMES-LABEL: FPNames:
+; FULLNAMES: # %bb.0: # %entry
+; FULLNAMES-NEXT: xsadddp f1, f1, f2
+; FULLNAMES-NEXT: blr
+;
+; NOFULLNAMES-LABEL: FPNames:
+; NOFULLNAMES: # %bb.0: # %entry
+; NOFULLNAMES-NEXT: xsadddp 1, 1, 2
+; NOFULLNAMES-NEXT: blr
+entry:
+ %add = fadd double %a, %b
+ ret double %add
+}
+
+define dso_local <4 x float> @VecNames(<4 x float> noundef %a, <4 x float> noundef %b) local_unnamed_addr #0 {
+; FULLNAMES-LABEL: VecNames:
+; FULLNAMES: # %bb.0: # %entry
+; FULLNAMES-NEXT: xvaddsp vs34, vs34, vs35
+; FULLNAMES-NEXT: blr
+;
+; NOFULLNAMES-LABEL: VecNames:
+; NOFULLNAMES: # %bb.0: # %entry
+; NOFULLNAMES-NEXT: xvaddsp 34, 34, 35
+; NOFULLNAMES-NEXT: blr
+entry:
+ %add = fadd <4 x float> %a, %b
+ ret <4 x float> %add
+}
+
+attributes #0 = { nounwind willreturn "target-features"="+altivec" }
>From c4a82eb8dfb7bce631f650360f8aeb01a5e74de0 Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 25 Oct 2023 18:21:39 -0500
Subject: [PATCH 2/7] Missed a little cleanup on a couple of source files.
---
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 7 ++-----
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h | 3 +--
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index 17498627a84fdfd..bab3089aeb9892c 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -613,11 +613,8 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
/// getVerboseConditionalRegName - This method expands the condition register
/// when requested explicitly or targetting Darwin.
-const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
- unsigned RegEncoding,
- const MCSubtargetInfo &STI)
- const {
- // __SP__
+const char *PPCInstPrinter::getVerboseConditionRegName(
+ unsigned RegNum, unsigned RegEncoding, const MCSubtargetInfo &STI) const {
if (!FullRegNames && !STI.hasFeature(PPC::FeatureFullRegisterNames))
return nullptr;
if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
index 2e29971a20fc593..a75ae3b400a2813 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
@@ -23,8 +23,7 @@ class PPCInstPrinter : public MCInstPrinter {
private:
bool showRegistersWithPercentPrefix(const char *RegName) const;
bool showRegistersWithPrefix(const MCSubtargetInfo &STI) const;
- const char *getVerboseConditionRegName(unsigned RegNum,
- unsigned RegEncoding,
+ const char *getVerboseConditionRegName(unsigned RegNum, unsigned RegEncoding,
const MCSubtargetInfo &STI) const;
public:
>From 96064c869118e9b495339e667a46e7d0f482ef46 Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 1 Nov 2023 14:56:32 -0500
Subject: [PATCH 3/7] Changed the patch to use CodeGenOpts instead of target
features.
I simplified the clang test significantly.
I also completely removed the llc test. Since the code gen opt is now internal
there is no good way that I know of to test it using llc.
---
clang/include/clang/Basic/CodeGenOptions.def | 1 +
clang/include/clang/Driver/Options.td | 10 ++-
clang/lib/Basic/Targets/PPC.cpp | 6 --
clang/lib/Basic/Targets/PPC.h | 1 -
clang/lib/CodeGen/BackendUtil.cpp | 1 +
clang/lib/Driver/ToolChains/Clang.cpp | 6 ++
clang/lib/Frontend/CompilerInvocation.cpp | 3 +
.../test/CodeGen/PowerPC/ppc-full-reg-names.c | 78 +++----------------
llvm/include/llvm/MC/MCAsmInfo.h | 6 ++
llvm/include/llvm/MC/MCTargetOptions.h | 3 +
llvm/lib/CodeGen/LLVMTargetMachine.cpp | 2 +
llvm/lib/MC/MCAsmInfo.cpp | 1 +
llvm/lib/MC/MCTargetOptions.cpp | 2 +-
.../PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 13 ++--
.../PowerPC/MCTargetDesc/PPCInstPrinter.h | 6 +-
llvm/lib/Target/PowerPC/PPC.td | 4 -
.../CodeGen/PowerPC/ppc-full-reg-names.ll | 62 ---------------
17 files changed, 50 insertions(+), 155 deletions(-)
delete mode 100644 llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll
diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def
index d7588fd430764cb..22658a01163261e 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -197,6 +197,7 @@ CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///< -fno-hip-fp32-correctly-rounde
CODEGENOPT(HIPSaveKernelArgName, 1, 0) ///< Set when -fhip-kernel-arg-name is enabled.
CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get unique names.
CODEGENOPT(SplitMachineFunctions, 1, 0) ///< Split machine functions using profile information.
+CODEGENOPT(UseFullRegisterNames, 1, 0) ///< Print full register names in assembly -mregnames
/// When false, this attempts to generate code as if the result of an
/// overflowing conversion matches the overflowing behavior of a target's native
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 339966a36b513bc..d74c9dc96a751bb 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4777,10 +4777,12 @@ def mrop_protect : Flag<["-"], "mrop-protect">,
Group<m_ppc_Features_Group>;
def mprivileged : Flag<["-"], "mprivileged">,
Group<m_ppc_Features_Group>;
-def mregnames : Flag<["-"], "mregnames">, Group<m_ppc_Features_Group>,
- Visibility<[ClangOption]>;
-def mno_regnames : Flag<["-"], "mno-regnames">, Group<m_ppc_Features_Group>,
- Visibility<[ClangOption]>;
+
+defm regnames : BoolOption<"m", "regnames",
+ CodeGenOpts<"UseFullRegisterNames">, DefaultFalse,
+ PosFlag<SetTrue, [], [ClangOption, CC1Option], "Use full register names when writing assembly output">,
+ NegFlag<SetFalse, [], [ClangOption], "Use only register numbers when writing assembly output">>,
+ Group<m_Group>;
} // let Flags = [TargetSpecific]
def maix_small_local_exec_tls : Flag<["-"], "maix-small-local-exec-tls">,
Group<m_ppc_Features_Group>,
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 211d9a0295c9ad9..5ce276e1af9ef64 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -89,8 +89,6 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
IsISA3_1 = true;
} else if (Feature == "+quadword-atomics") {
HasQuadwordAtomics = true;
- } else if (Feature == "+regnames") {
- FullRegisterNames = true;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@@ -553,9 +551,6 @@ bool PPCTargetInfo::initFeatureMap(
// off by default.
Features["aix-small-local-exec-tls"] = false;
- // By default full register names are not used in assembly.
- Features["regnames"] = false;
-
Features["spe"] = llvm::StringSwitch<bool>(CPU)
.Case("8548", true)
.Case("e500", true)
@@ -705,7 +700,6 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Case("isa-v30-instructions", IsISA3_0)
.Case("isa-v31-instructions", IsISA3_1)
.Case("quadword-atomics", HasQuadwordAtomics)
- .Case("regnames", FullRegisterNames)
.Default(false);
}
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ddef057bb306cad..4d62673ba7fb8c5 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -80,7 +80,6 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
- bool FullRegisterNames = false;
protected:
std::string ABI;
diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
index 70accce456d3c07..34fbe127b8df3a2 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -488,6 +488,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
Options.MCOptions.Argv0 = CodeGenOpts.Argv0;
Options.MCOptions.CommandLineArgs = CodeGenOpts.CommandLineArgs;
Options.MCOptions.AsSecureLogFile = CodeGenOpts.AsSecureLogFile;
+ Options.MCOptions.UseFullRegisterNames = CodeGenOpts.UseFullRegisterNames;
Options.MisExpect = CodeGenOpts.MisExpect;
return true;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 79f7fba22570746..67aedf5d284506a 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5011,6 +5011,12 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
Args.AddLastArg(CmdArgs, options::OPT_fthinlto_index_EQ);
}
+ if (const Arg *A = Args.getLastArg(options::OPT_mregnames,
+ options::OPT_mno_regnames)) {
+ if (A->getOption().matches(options::OPT_mregnames))
+ Args.AddLastArg(CmdArgs, options::OPT_mregnames);
+ }
+
if (Args.getLastArg(options::OPT_fthin_link_bitcode_EQ))
Args.AddLastArg(CmdArgs, options::OPT_fthin_link_bitcode_EQ);
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 637c6a35af6532b..cbba5583beb5e65 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -1780,6 +1780,9 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args,
Opts.setDebugInfo(llvm::codegenoptions::LimitedDebugInfo);
}
+ if (const Arg *A = Args.getLastArg(OPT_mregnames))
+ Opts.UseFullRegisterNames = true;
+
for (const auto &Arg : Args.getAllArgValues(OPT_fdebug_prefix_map_EQ)) {
auto Split = StringRef(Arg).split('=');
Opts.DebugPrefixMap.emplace_back(Split.first, Split.second);
diff --git a/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
index c1bd22c1134c9a7..aaf722213dc4a07 100644
--- a/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
+++ b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
@@ -1,78 +1,20 @@
// REQUIRES: powerpc-registered-target
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: %clang -### -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -mregnames \
// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: %clang -### -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -mregnames \
// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \
+// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -mregnames \
// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: %clang -### -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -mno-regnames \
// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: %clang -### -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -mno-regnames \
// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \
+// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -mno-regnames \
// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
-// Also check the assembly to make sure that the full names are used.
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mregnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES
-// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
-// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mno-regnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES
-
-
-
-// FULLNAMES-LABEL: @IntNames
-// FULLNAMES-SAME: #0
-// NOFULLNAMES-LABEL: @IntNames
-// NOFULLNAMES-SAME: #0
-// ASMFULLNAMES-LABEL: IntNames:
-// ASMFULLNAMES: add r3, r4, r3
-// ASMFULLNAMES: blr
-// ASMNOFULLNAMES-LABEL: IntNames:
-// ASMNOFULLNAMES: add 3, 4, 3
-// ASMNOFULLNAMES: blr
-int IntNames(int a, int b) {
- return a + b;
-}
-
-// FULLNAMES-LABEL: @FPNames
-// FULLNAMES-SAME: #0
-// NOFULLNAMES-LABEL: @FPNames
-// NOFULLNAMES-SAME: #0
-// ASMFULLNAMES-LABEL: FPNames:
-// ASMFULLNAMES: xsadddp f1, f1, f2
-// ASMFULLNAMES: blr
-// ASMNOFULLNAMES-LABEL: FPNames:
-// ASMNOFULLNAMES: xsadddp 1, 1, 2
-// ASMNOFULLNAMES: blr
-double FPNames(double a, double b) {
- return a + b;
-}
-
-// FULLNAMES-LABEL: @VecNames
-// FULLNAMES-SAME: #0
-// NOFULLNAMES-LABEL: @VecNames
-// NOFULLNAMES-SAME: #0
-// ASMFULLNAMES-LABEL: VecNames:
-// ASMFULLNAMES: xvaddsp vs34, vs34, vs35
-// ASMFULLNAMES: blr
-// ASMNOFULLNAMES-LABEL: VecNames:
-// ASMNOFULLNAMES: xvaddsp 34, 34, 35
-// ASMNOFULLNAMES: blr
-vector float VecNames(vector float a, vector float b) {
- return a + b;
-}
-
-// FULLNAMES: attributes #0 = {
-// FULLNAMES-SAME: +regnames
-// NOFULLNAMES: attributes #0 = {
-// NOFULLNAMES-SAME: -regnames
+// FULLNAMES: clang
+// FULLNAMES-SAME: -mregnames
+// NOFULLNAMES: clang
+// NOFULLNAMES-SAME-NOT: -mregnames
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h
index c28cd12112358c7..4ac0eb89d850407 100644
--- a/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/llvm/include/llvm/MC/MCAsmInfo.h
@@ -240,6 +240,9 @@ class MCAsmInfo {
/// True if the target supports LEB128 directives.
bool HasLEB128Directives = true;
+ /// True if full register names are printed.
+ bool UseFullRegisterNames = false;
+
//===--- Data Emission Directives -------------------------------------===//
/// This should be set to the directive used to get some number of zero (and
@@ -710,6 +713,9 @@ class MCAsmInfo {
bool hasLEB128Directives() const { return HasLEB128Directives; }
+ bool useFullRegisterNames() const { return UseFullRegisterNames; }
+ void setFullRegisterNames(bool V) { UseFullRegisterNames = V; }
+
const char *getZeroDirective() const { return ZeroDirective; }
bool doesZeroDirectiveSupportNonZeroValue() const {
return ZeroDirectiveSupportsNonZeroValue;
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h b/llvm/include/llvm/MC/MCTargetOptions.h
index 9fc1e07d085ebaa..e2d18041c3baa13 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -89,6 +89,9 @@ class MCTargetOptions {
// functions on Darwins.
bool EmitCompactUnwindNonCanonical : 1;
+ // Whether or not to use full register names on PowerPC.
+ bool UseFullRegisterNames : 1;
+
MCTargetOptions();
/// getABIName - If this returns a non-empty string this represents the
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index 87a17b88db12433..4f4566b8add170a 100644
--- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -81,6 +81,8 @@ void LLVMTargetMachine::initAsmInfo() {
TmpAsmInfo->setRelaxELFRelocations(Options.RelaxELFRelocations);
+ TmpAsmInfo->setFullRegisterNames(Options.MCOptions.UseFullRegisterNames);
+
if (Options.ExceptionModel != ExceptionHandling::None)
TmpAsmInfo->setExceptionsType(Options.ExceptionModel);
diff --git a/llvm/lib/MC/MCAsmInfo.cpp b/llvm/lib/MC/MCAsmInfo.cpp
index 1675e24301dc69c..e4ace2de864d6b5 100644
--- a/llvm/lib/MC/MCAsmInfo.cpp
+++ b/llvm/lib/MC/MCAsmInfo.cpp
@@ -67,6 +67,7 @@ MCAsmInfo::MCAsmInfo() {
UseIntegratedAssembler = true;
ParseInlineAsmUsingAsmParser = false;
PreserveAsmComments = true;
+ UseFullRegisterNames = false;
}
MCAsmInfo::~MCAsmInfo() = default;
diff --git a/llvm/lib/MC/MCTargetOptions.cpp b/llvm/lib/MC/MCTargetOptions.cpp
index 8fea8c7715bdc81..6dc280176cd51cc 100644
--- a/llvm/lib/MC/MCTargetOptions.cpp
+++ b/llvm/lib/MC/MCTargetOptions.cpp
@@ -19,7 +19,7 @@ MCTargetOptions::MCTargetOptions()
PreserveAsmComments(true), Dwarf64(false),
EmitDwarfUnwind(EmitDwarfUnwindType::Default),
MCUseDwarfDirectory(DefaultDwarfDirectory),
- EmitCompactUnwindNonCanonical(false) {}
+ EmitCompactUnwindNonCanonical(false), UseFullRegisterNames(false) {}
StringRef MCTargetOptions::getABIName() const {
return ABIName;
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index bab3089aeb9892c..ea9721c9159d4a2 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -13,6 +13,7 @@
#include "MCTargetDesc/PPCInstPrinter.h"
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
@@ -614,8 +615,8 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
/// getVerboseConditionalRegName - This method expands the condition register
/// when requested explicitly or targetting Darwin.
const char *PPCInstPrinter::getVerboseConditionRegName(
- unsigned RegNum, unsigned RegEncoding, const MCSubtargetInfo &STI) const {
- if (!FullRegNames && !STI.hasFeature(PPC::FeatureFullRegisterNames))
+ unsigned RegNum, unsigned RegEncoding) const {
+ if (!FullRegNames && !MAI.useFullRegisterNames())
return nullptr;
if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
return nullptr;
@@ -634,9 +635,9 @@ const char *PPCInstPrinter::getVerboseConditionRegName(
// showRegistersWithPrefix - This method determines whether registers
// should be number-only or include the prefix.
-bool PPCInstPrinter::showRegistersWithPrefix(const MCSubtargetInfo &STI) const {
+bool PPCInstPrinter::showRegistersWithPrefix() const {
return FullRegNamesWithPercent || FullRegNames ||
- STI.hasFeature(PPC::FeatureFullRegisterNames);
+ MAI.useFullRegisterNames();
}
void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -648,12 +649,12 @@ void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo);
const char *RegName;
- RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg), STI);
+ RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
if (RegName == nullptr)
RegName = getRegisterName(Reg);
if (showRegistersWithPercentPrefix(RegName))
O << "%";
- if (!showRegistersWithPrefix(STI))
+ if (!showRegistersWithPrefix())
RegName = PPC::stripRegisterPrefix(RegName);
O << RegName;
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
index a75ae3b400a2813..6ba3eb4c79dc990 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
@@ -22,9 +22,9 @@ class PPCInstPrinter : public MCInstPrinter {
Triple TT;
private:
bool showRegistersWithPercentPrefix(const char *RegName) const;
- bool showRegistersWithPrefix(const MCSubtargetInfo &STI) const;
- const char *getVerboseConditionRegName(unsigned RegNum, unsigned RegEncoding,
- const MCSubtargetInfo &STI) const;
+ bool showRegistersWithPrefix() const;
+ const char *getVerboseConditionRegName(unsigned RegNum,
+ unsigned RegEncoding) const;
public:
PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 568a3d4b5a2aab1..535616d33a8032a 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -338,10 +338,6 @@ def FeaturePredictableSelectIsExpensive :
def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
"MFLR is a fast instruction">;
-def FeatureFullRegisterNames :
- SubtargetFeature<"regnames", "FullRegisterNames", "true",
- "Use full register names in assembly.">;
-
// Since new processors generally contain a superset of features of those that
// came before them, the idea is to make implementations of new processors
// less error prone and easier to read.
diff --git a/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll b/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll
deleted file mode 100644
index cb0dcaf7566bcdd..000000000000000
--- a/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll
+++ /dev/null
@@ -1,62 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
-; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu < %s \
-; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
-; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
-; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu < %s \
-; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
-; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s
-
-
-define dso_local signext i32 @IntNames(i32 noundef signext %a, i32 noundef signext %b) local_unnamed_addr #0 {
-; FULLNAMES-LABEL: IntNames:
-; FULLNAMES: # %bb.0: # %entry
-; FULLNAMES-NEXT: add r3, r4, r3
-; FULLNAMES-NEXT: extsw r3, r3
-; FULLNAMES-NEXT: blr
-;
-; NOFULLNAMES-LABEL: IntNames:
-; NOFULLNAMES: # %bb.0: # %entry
-; NOFULLNAMES-NEXT: add 3, 4, 3
-; NOFULLNAMES-NEXT: extsw 3, 3
-; NOFULLNAMES-NEXT: blr
-entry:
- %add = add nsw i32 %b, %a
- ret i32 %add
-}
-
-define dso_local double @FPNames(double noundef %a, double noundef %b) local_unnamed_addr #0 {
-; FULLNAMES-LABEL: FPNames:
-; FULLNAMES: # %bb.0: # %entry
-; FULLNAMES-NEXT: xsadddp f1, f1, f2
-; FULLNAMES-NEXT: blr
-;
-; NOFULLNAMES-LABEL: FPNames:
-; NOFULLNAMES: # %bb.0: # %entry
-; NOFULLNAMES-NEXT: xsadddp 1, 1, 2
-; NOFULLNAMES-NEXT: blr
-entry:
- %add = fadd double %a, %b
- ret double %add
-}
-
-define dso_local <4 x float> @VecNames(<4 x float> noundef %a, <4 x float> noundef %b) local_unnamed_addr #0 {
-; FULLNAMES-LABEL: VecNames:
-; FULLNAMES: # %bb.0: # %entry
-; FULLNAMES-NEXT: xvaddsp vs34, vs34, vs35
-; FULLNAMES-NEXT: blr
-;
-; NOFULLNAMES-LABEL: VecNames:
-; NOFULLNAMES: # %bb.0: # %entry
-; NOFULLNAMES-NEXT: xvaddsp 34, 34, 35
-; NOFULLNAMES-NEXT: blr
-entry:
- %add = fadd <4 x float> %a, %b
- ret <4 x float> %add
-}
-
-attributes #0 = { nounwind willreturn "target-features"="+altivec" }
>From 8d9696941b8ec0ad8fe9f4d04d6d129dc1f18d08 Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 1 Nov 2023 15:07:26 -0500
Subject: [PATCH 4/7] Fixed the broken test case.
---
.../test/CodeGen/PowerPC/ppc-full-reg-names.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
index aaf722213dc4a07..aac15d7ae922945 100644
--- a/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
+++ b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c
@@ -1,20 +1,18 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang -### -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -mregnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
+// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=FULLNAMES
// RUN: %clang -### -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -mregnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
+// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=FULLNAMES
// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -mregnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES
+// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=FULLNAMES
// RUN: %clang -### -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -mno-regnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
+// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=NOFULLNAMES
// RUN: %clang -### -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -mno-regnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
+// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=NOFULLNAMES
// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -mno-regnames \
-// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES
+// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=NOFULLNAMES
-// FULLNAMES: clang
-// FULLNAMES-SAME: -mregnames
-// NOFULLNAMES: clang
-// NOFULLNAMES-SAME-NOT: -mregnames
+// FULLNAMES: -mregnames
+// NOFULLNAMES-NOT: -mregnames
>From f39d293dbbd29172dac6ddc2a43e191db7699de0 Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 1 Nov 2023 20:48:58 -0500
Subject: [PATCH 5/7] Fixed the formatting.
---
clang/lib/Driver/ToolChains/Clang.cpp | 4 ++--
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 67aedf5d284506a..c043215284481d4 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5011,8 +5011,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
Args.AddLastArg(CmdArgs, options::OPT_fthinlto_index_EQ);
}
- if (const Arg *A = Args.getLastArg(options::OPT_mregnames,
- options::OPT_mno_regnames)) {
+ if (const Arg *A =
+ Args.getLastArg(options::OPT_mregnames, options::OPT_mno_regnames)) {
if (A->getOption().matches(options::OPT_mregnames))
Args.AddLastArg(CmdArgs, options::OPT_mregnames);
}
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index ea9721c9159d4a2..b0a060e1e224a48 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -614,8 +614,9 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
/// getVerboseConditionalRegName - This method expands the condition register
/// when requested explicitly or targetting Darwin.
-const char *PPCInstPrinter::getVerboseConditionRegName(
- unsigned RegNum, unsigned RegEncoding) const {
+const char *
+PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
+ unsigned RegEncoding) const {
if (!FullRegNames && !MAI.useFullRegisterNames())
return nullptr;
if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
@@ -636,8 +637,7 @@ const char *PPCInstPrinter::getVerboseConditionRegName(
// showRegistersWithPrefix - This method determines whether registers
// should be number-only or include the prefix.
bool PPCInstPrinter::showRegistersWithPrefix() const {
- return FullRegNamesWithPercent || FullRegNames ||
- MAI.useFullRegisterNames();
+ return FullRegNamesWithPercent || FullRegNames || MAI.useFullRegisterNames();
}
void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
>From efa37227fc8f36b32bf59923b1acdf7c13360734 Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Thu, 2 Nov 2023 10:21:10 -0500
Subject: [PATCH 6/7] Added PPC to variable name and added isPPC() guard.
---
clang/include/clang/Basic/CodeGenOptions.def | 2 +-
clang/include/clang/Driver/Options.td | 2 +-
clang/lib/CodeGen/BackendUtil.cpp | 3 ++-
clang/lib/Driver/ToolChains/Clang.cpp | 10 +++++-----
clang/lib/Frontend/CompilerInvocation.cpp | 2 +-
llvm/include/llvm/MC/MCAsmInfo.h | 6 +++---
llvm/include/llvm/MC/MCTargetOptions.h | 2 +-
llvm/lib/CodeGen/LLVMTargetMachine.cpp | 2 +-
llvm/lib/MC/MCAsmInfo.cpp | 2 +-
llvm/lib/MC/MCTargetOptions.cpp | 2 +-
10 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def
index 22658a01163261e..cb04c15c069bf73 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -197,7 +197,7 @@ CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///< -fno-hip-fp32-correctly-rounde
CODEGENOPT(HIPSaveKernelArgName, 1, 0) ///< Set when -fhip-kernel-arg-name is enabled.
CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get unique names.
CODEGENOPT(SplitMachineFunctions, 1, 0) ///< Split machine functions using profile information.
-CODEGENOPT(UseFullRegisterNames, 1, 0) ///< Print full register names in assembly -mregnames
+CODEGENOPT(PPCUseFullRegisterNames, 1, 0) ///< Print full register names in assembly -mregnames
/// When false, this attempts to generate code as if the result of an
/// overflowing conversion matches the overflowing behavior of a target's native
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index d74c9dc96a751bb..34ac2531922568e 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4779,7 +4779,7 @@ def mprivileged : Flag<["-"], "mprivileged">,
Group<m_ppc_Features_Group>;
defm regnames : BoolOption<"m", "regnames",
- CodeGenOpts<"UseFullRegisterNames">, DefaultFalse,
+ CodeGenOpts<"PPCUseFullRegisterNames">, DefaultFalse,
PosFlag<SetTrue, [], [ClangOption, CC1Option], "Use full register names when writing assembly output">,
NegFlag<SetFalse, [], [ClangOption], "Use only register numbers when writing assembly output">>,
Group<m_Group>;
diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
index 34fbe127b8df3a2..06bd0ad059835cf 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -488,7 +488,8 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
Options.MCOptions.Argv0 = CodeGenOpts.Argv0;
Options.MCOptions.CommandLineArgs = CodeGenOpts.CommandLineArgs;
Options.MCOptions.AsSecureLogFile = CodeGenOpts.AsSecureLogFile;
- Options.MCOptions.UseFullRegisterNames = CodeGenOpts.UseFullRegisterNames;
+ Options.MCOptions.PPCUseFullRegisterNames =
+ CodeGenOpts.PPCUseFullRegisterNames;
Options.MisExpect = CodeGenOpts.MisExpect;
return true;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index c043215284481d4..69d7b92ffea3825 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5011,11 +5011,11 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
Args.AddLastArg(CmdArgs, options::OPT_fthinlto_index_EQ);
}
- if (const Arg *A =
- Args.getLastArg(options::OPT_mregnames, options::OPT_mno_regnames)) {
- if (A->getOption().matches(options::OPT_mregnames))
- Args.AddLastArg(CmdArgs, options::OPT_mregnames);
- }
+ if (Triple.isPPC())
+ if (const Arg *A =
+ Args.getLastArg(options::OPT_mregnames, options::OPT_mno_regnames))
+ if (A->getOption().matches(options::OPT_mregnames))
+ Args.AddLastArg(CmdArgs, options::OPT_mregnames);
if (Args.getLastArg(options::OPT_fthin_link_bitcode_EQ))
Args.AddLastArg(CmdArgs, options::OPT_fthin_link_bitcode_EQ);
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index cbba5583beb5e65..2f64d8bd3937237 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -1781,7 +1781,7 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args,
}
if (const Arg *A = Args.getLastArg(OPT_mregnames))
- Opts.UseFullRegisterNames = true;
+ Opts.PPCUseFullRegisterNames = true;
for (const auto &Arg : Args.getAllArgValues(OPT_fdebug_prefix_map_EQ)) {
auto Split = StringRef(Arg).split('=');
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h
index 4ac0eb89d850407..a3c9b19e859d938 100644
--- a/llvm/include/llvm/MC/MCAsmInfo.h
+++ b/llvm/include/llvm/MC/MCAsmInfo.h
@@ -241,7 +241,7 @@ class MCAsmInfo {
bool HasLEB128Directives = true;
/// True if full register names are printed.
- bool UseFullRegisterNames = false;
+ bool PPCUseFullRegisterNames = false;
//===--- Data Emission Directives -------------------------------------===//
@@ -713,8 +713,8 @@ class MCAsmInfo {
bool hasLEB128Directives() const { return HasLEB128Directives; }
- bool useFullRegisterNames() const { return UseFullRegisterNames; }
- void setFullRegisterNames(bool V) { UseFullRegisterNames = V; }
+ bool useFullRegisterNames() const { return PPCUseFullRegisterNames; }
+ void setFullRegisterNames(bool V) { PPCUseFullRegisterNames = V; }
const char *getZeroDirective() const { return ZeroDirective; }
bool doesZeroDirectiveSupportNonZeroValue() const {
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h b/llvm/include/llvm/MC/MCTargetOptions.h
index e2d18041c3baa13..afb329eb6f935ec 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -90,7 +90,7 @@ class MCTargetOptions {
bool EmitCompactUnwindNonCanonical : 1;
// Whether or not to use full register names on PowerPC.
- bool UseFullRegisterNames : 1;
+ bool PPCUseFullRegisterNames : 1;
MCTargetOptions();
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index 4f4566b8add170a..42cabb58e5189d5 100644
--- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -81,7 +81,7 @@ void LLVMTargetMachine::initAsmInfo() {
TmpAsmInfo->setRelaxELFRelocations(Options.RelaxELFRelocations);
- TmpAsmInfo->setFullRegisterNames(Options.MCOptions.UseFullRegisterNames);
+ TmpAsmInfo->setFullRegisterNames(Options.MCOptions.PPCUseFullRegisterNames);
if (Options.ExceptionModel != ExceptionHandling::None)
TmpAsmInfo->setExceptionsType(Options.ExceptionModel);
diff --git a/llvm/lib/MC/MCAsmInfo.cpp b/llvm/lib/MC/MCAsmInfo.cpp
index e4ace2de864d6b5..290be40371663fb 100644
--- a/llvm/lib/MC/MCAsmInfo.cpp
+++ b/llvm/lib/MC/MCAsmInfo.cpp
@@ -67,7 +67,7 @@ MCAsmInfo::MCAsmInfo() {
UseIntegratedAssembler = true;
ParseInlineAsmUsingAsmParser = false;
PreserveAsmComments = true;
- UseFullRegisterNames = false;
+ PPCUseFullRegisterNames = false;
}
MCAsmInfo::~MCAsmInfo() = default;
diff --git a/llvm/lib/MC/MCTargetOptions.cpp b/llvm/lib/MC/MCTargetOptions.cpp
index 6dc280176cd51cc..07c6e752cb613d0 100644
--- a/llvm/lib/MC/MCTargetOptions.cpp
+++ b/llvm/lib/MC/MCTargetOptions.cpp
@@ -19,7 +19,7 @@ MCTargetOptions::MCTargetOptions()
PreserveAsmComments(true), Dwarf64(false),
EmitDwarfUnwind(EmitDwarfUnwindType::Default),
MCUseDwarfDirectory(DefaultDwarfDirectory),
- EmitCompactUnwindNonCanonical(false), UseFullRegisterNames(false) {}
+ EmitCompactUnwindNonCanonical(false), PPCUseFullRegisterNames(false) {}
StringRef MCTargetOptions::getABIName() const {
return ABIName;
>From 14fd698731ebbf5b18f4ecc9522c4720c49c0228 Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Fri, 3 Nov 2023 22:38:37 -0500
Subject: [PATCH 7/7] Have the mregnames option also add the percent char as
that is what GCC does as well.
---
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index b0a060e1e224a48..ccbb650c65365b4 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -597,7 +597,8 @@ void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
/// showRegistersWithPercentPrefix - Check if this register name should be
/// printed with a percentage symbol as prefix.
bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
- if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX)
+ if ((!FullRegNamesWithPercent && !MAI.useFullRegisterNames()) ||
+ TT.getOS() == Triple::AIX)
return false;
switch (RegName[0]) {
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