[llvm] [clang] [AArch64][SVE2.1] Add intrinsics for quadword loads/stores with unscaled offset (PR #70474)

[David Sherwood via cfe-commits]

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@@ -9671,28 +9677,47 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const CallExpr *E,
   // The vector type that is returned may be different from the
   // eventual type loaded from memory.
   auto VectorTy = cast<llvm::ScalableVectorType>(ReturnTy);
-  auto MemoryTy = llvm::ScalableVectorType::get(MemEltTy, VectorTy);
+  llvm::ScalableVectorType *MemoryTy = nullptr;
+  llvm::ScalableVectorType *PredTy = nullptr;
+  bool IsExtendingLoad = true;
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david-arm wrote:

I personally think using this variable is misleading because aarch64_sve_ld1uwq is actually an extending load - we're extending from 32-bit memory elements to 128-bit integer elements. So it looks odd when we set this to false. Perhaps it's better to just explicitly have a variable called `IsQuadLoad` and use that instead rather than try to generalise this. The quad-word loads are a really just an exception here because we're working around the lack of a <vscale x 1 x i128> type. So you'd have something like

  case Intrinsic::aarch64_sve_ld1uwq:
    IsQuadLoad = true;
    ...
  default:
    IsQuadLoad = false;


  Function *F =
      CGM.getIntrinsic(IntrinsicID, IsQuadLoad ? VectorTy : MemoryTy);\

...

  if (IsQuadLoad)
    return Load;

https://github.com/llvm/llvm-project/pull/70474