[clang] [llvm] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

[Shao-Ce SUN via cfe-commits]

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@@ -0,0 +1,307 @@
+//==- RISCVSchedXiangShanNanHu.td - XiangShan-NanHu Scheduling Definitions --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-------------------------------------------------------------------------------------===//
+
+//===-------------------------------------------------------------------------------------===//
+
+// XiangShan is a high-performance open-source RISC-V processor developed by
+// the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences.
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sunshaoce wrote:

I think this should be a more formal name:
`the Institute of Computing Technology (ICT), Chinese Academy of Sciences`

https://github.com/llvm/llvm-project/pull/70232