[llvm] [clang] [AArch64][SME] Remove immediate argument restriction for svldr and svstr (PR #68565)

[Sam Tebbs via cfe-commits]

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@@ -1741,6 +1742,54 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N, unsigned NumVecs,
   CurDAG->RemoveDeadNode(N);
 }
 
+void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
+  // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+  // If the vector select parameter is an immediate in the range 0-15 then we
+  // can emit it directly into the instruction as it's a legal operand.
+  // Otherwise we must emit 0 as the vector select operand and modify the base
+  // register instead.
+  SDLoc DL(N);
+
+  SDValue VecNum = N->getOperand(4), Base = N->getOperand(3),
+          TileSlice = N->getOperand(2);
+  int Imm = -1;
+  if (auto ImmNode = dyn_cast<ConstantSDNode>(VecNum))
+    Imm = ImmNode->getZExtValue();
+
+  if (Imm >= 0 && Imm <= 15) {
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SamTebbs33 wrote:

> Something still needs to happen with the immediate argument when it doesn't fit entirely into the instruction's immediate operand. The current result is not correct.

I don't quite understand what that something is if immediate if it doesn't fit in the range. Currently the immediate is multiplied by svl and added to the base register if it doesn't fit. What else should be done if it doesn't fit in the range?

> Maybe you can restructure the code in such a way that it first tries to fold as much of the constant into the instruction's immediate operand, and then adds the remainder to the tile-slice and to the pointer (multiplied by SVL), as you do in the code below.

Do you mean that if, for example, we have an immediate vecnum of 17, then we put 15 into the offset field of the instruction and add 2 x SVL to the base and slice registers? Naively I don't see that being an improvement as you're doing the multiplication in two places (ldr instruction and an extra madd) rather than one.



https://github.com/llvm/llvm-project/pull/68565