[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

Mon Oct 30 01:00:46 PDT 2023

wangpc added a comment.

In D70401#4655408 <https://reviews.llvm.org/D70401#4655408>, @asb wrote:

> First of all, thank you to everyone who has been trying to nudge this forward and apologies it must have been a frustrating experience.
>
> I appreciate there are users who want to see this and I don't like that LLVM doesn't serve them right now - I think it's unfortunate that this need for the ABI hasn't translated into effort to finalise the ABI definition in the psABI doc and to at least get it to match what GCC actually implements (spec. That said, I've not really vocalised that concern clearly up to now - so that's my bad.
>
> Matching what GCC does by setting stack alignment to 4 bytes for 2xlen types seems fine - except this doesn't seem to be documented explicitly in the current ABI doc (it notes the stack if 4 byte aligned, but you could have that be the case and still require it to be realigned when storing objects with a greater alignment requirement, surely?).
>
> Having different alignment requirements _only_ on the stack does seem ugly, but I can't think of something off hand that would realistically break with this.
>
> @wangpc do you want to update this with the suggested documentation in the release notes and RISCVUsage on the support being "experimental"?

Thanks! I added a note to the RISCVUsage. There won't be `experimental-e` like other experimental extensions as it is already ratified and adds no instruction, it is experimental just because the support is experimental.

For ABI part, I don't know if @kito-cheng has some updates/comments.

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https://reviews.llvm.org/D70401