[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

[Michael Maitland via cfe-commits]

================
@@ -78,7 +78,7 @@ def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
 } // Predicates = [HasStdExtD]
 
 foreach Ext = DExts in {
-  let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
+  let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in {
----------------
michaelmaitland wrote:

Should this change be in a separate commit?

https://github.com/llvm/llvm-project/pull/70232