[clang] c2f02e3 - Clang: Define macro _MIPS_SPFPSET
Brad Smith via cfe-commits
cfe-commits at lists.llvm.org
Sat Oct 21 04:16:07 PDT 2023
Author: Brad Smith
Date: 2023-10-21T07:08:54-04:00
New Revision: c2f02e3bd6a5b287a221ae9038e6727abc3e6652
URL: https://github.com/llvm/llvm-project/commit/c2f02e3bd6a5b287a221ae9038e6727abc3e6652
DIFF: https://github.com/llvm/llvm-project/commit/c2f02e3bd6a5b287a221ae9038e6727abc3e6652.diff
LOG: Clang: Define macro _MIPS_SPFPSET
GCC defines this macro for how many single-precision floating point registers
can be used.
If the -mno-odd-spreg option is given, it will be 16; if either -mno-odd-spreg
nor -modd-spreg are given, we set it to 16 for FPXX.
Reviewed By: theraven
Differential Revision: https://reviews.llvm.org/D157896
Added:
Modified:
clang/lib/Basic/Targets/Mips.cpp
clang/lib/Basic/Targets/Mips.h
clang/test/Preprocessor/init-mips.c
Removed:
################################################################################
diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index cdf652c49f603e3..bc90d1b93d53f6d 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -149,6 +149,10 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("_MIPS_FPSET", Twine(32));
else
Builder.defineMacro("_MIPS_FPSET", Twine(16));
+ if (NoOddSpreg)
+ Builder.defineMacro("_MIPS_SPFPSET", Twine(16));
+ else
+ Builder.defineMacro("_MIPS_SPFPSET", Twine(32));
if (IsMips16)
Builder.defineMacro("__mips16", Twine(1));
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index 7ecbd8633cb346b..f46b95abfd75c73 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -53,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
bool HasMSA;
bool DisableMadd4;
bool UseIndirectJumpHazard;
+ bool NoOddSpreg;
protected:
enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
@@ -313,6 +314,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
FloatABI = HardFloat;
DspRev = NoDSP;
FPMode = isFP64Default() ? FP64 : FPXX;
+ NoOddSpreg = false;
+ bool OddSpregGiven = false;
for (const auto &Feature : Features) {
if (Feature == "+single-float")
@@ -349,8 +352,18 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
IsNoABICalls = true;
else if (Feature == "+use-indirect-jump-hazard")
UseIndirectJumpHazard = true;
+ else if (Feature == "+nooddspreg") {
+ NoOddSpreg = true;
+ OddSpregGiven = false;
+ } else if (Feature == "-nooddspreg") {
+ NoOddSpreg = false;
+ OddSpregGiven = true;
+ }
}
+ if (FPMode == FPXX && !OddSpregGiven)
+ NoOddSpreg = true;
+
setDataLayout();
return true;
diff --git a/clang/test/Preprocessor/init-mips.c b/clang/test/Preprocessor/init-mips.c
index a07cee64e6848d2..34091ea3690dad0 100644
--- a/clang/test/Preprocessor/init-mips.c
+++ b/clang/test/Preprocessor/init-mips.c
@@ -10,6 +10,7 @@
// MIPS32BE:#define _MIPS_ARCH_MIPS32R2 1
// MIPS32BE:#define _MIPS_FPSET 16
// MIPS32BE:#define _MIPS_SIM _ABIO32
+// MIPS32BE:#define _MIPS_SPFPSET 16
// MIPS32BE:#define _MIPS_SZINT 32
// MIPS32BE:#define _MIPS_SZLONG 32
// MIPS32BE:#define _MIPS_SZPTR 32
@@ -220,6 +221,7 @@
// MIPS32EL:#define _MIPS_ARCH_MIPS32R2 1
// MIPS32EL:#define _MIPS_FPSET 16
// MIPS32EL:#define _MIPS_SIM _ABIO32
+// MIPS32EL:#define _MIPS_SPFPSET 16
// MIPS32EL:#define _MIPS_SZINT 32
// MIPS32EL:#define _MIPS_SZLONG 32
// MIPS32EL:#define _MIPS_SZPTR 32
@@ -432,6 +434,7 @@
// MIPSN32BE: #define _MIPS_FPSET 32
// MIPSN32BE: #define _MIPS_ISA _MIPS_ISA_MIPS64
// MIPSN32BE: #define _MIPS_SIM _ABIN32
+// MIPSN32BE: #define _MIPS_SPFPSET 32
// MIPSN32BE: #define _MIPS_SZINT 32
// MIPSN32BE: #define _MIPS_SZLONG 32
// MIPSN32BE: #define _MIPS_SZPTR 32
@@ -739,6 +742,7 @@
// MIPSN32EL: #define _MIPS_FPSET 32
// MIPSN32EL: #define _MIPS_ISA _MIPS_ISA_MIPS64
// MIPSN32EL: #define _MIPS_SIM _ABIN32
+// MIPSN32EL: #define _MIPS_SPFPSET 32
// MIPSN32EL: #define _MIPS_SZINT 32
// MIPSN32EL: #define _MIPS_SZLONG 32
// MIPSN32EL: #define _MIPS_SZPTR 32
@@ -1043,6 +1047,7 @@
// MIPS64BE:#define _MIPS_ARCH_MIPS64R2 1
// MIPS64BE:#define _MIPS_FPSET 32
// MIPS64BE:#define _MIPS_SIM _ABI64
+// MIPS64BE:#define _MIPS_SPFPSET 32
// MIPS64BE:#define _MIPS_SZINT 32
// MIPS64BE:#define _MIPS_SZLONG 64
// MIPS64BE:#define _MIPS_SZPTR 64
@@ -1253,6 +1258,7 @@
// MIPS64EL:#define _MIPS_ARCH_MIPS64R2 1
// MIPS64EL:#define _MIPS_FPSET 32
// MIPS64EL:#define _MIPS_SIM _ABI64
+// MIPS64EL:#define _MIPS_SPFPSET 32
// MIPS64EL:#define _MIPS_SZINT 32
// MIPS64EL:#define _MIPS_SZLONG 64
// MIPS64EL:#define _MIPS_SZPTR 64
@@ -1506,6 +1512,7 @@
// MIPS-ARCH-32R6:#define _MIPS_ARCH "mips32r6"
// MIPS-ARCH-32R6:#define _MIPS_ARCH_MIPS32R6 1
// MIPS-ARCH-32R6:#define _MIPS_ISA _MIPS_ISA_MIPS32
+// MIPS-ARCH-32R6:#define __mips_fpr 64
// MIPS-ARCH-32R6:#define __mips_isa_rev 6
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
@@ -1682,14 +1689,28 @@
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP %s
// MIPS32-NOFP:#define __mips_fpr 0
+// RUN: %clang_cc1 -target-feature -nooddspreg \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP-ODD %s
+// MIPS32-NOFP-ODD:#define _MIPS_SPFPSET 32
+// MIPS32-NOFP-ODD:#define __mips_fpr 0
+
+// RUN: %clang_cc1 -target-feature +nooddspreg -target-feature -fp64 \
+// RUN: -E -dM -triple=mips-none-none < /dev/null \
+// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-FP64-NOODD %s
+// MIPS32-FP64-NOODD:#define _MIPS_SPFPSET 16
+// MIPS32-FP64-NOODD:#define __mips_fpr 32
+
// RUN: %clang_cc1 -target-feature +fpxx \
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFPXX %s
+// MIPS32-MFPXX:#define _MIPS_SPFPSET 16
// MIPS32-MFPXX:#define __mips_fpr 0
// RUN: %clang_cc1 -target-cpu mips32r6 -target-feature +fpxx \
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32R6-MFPXX %s
+// MIPS32R6-MFPXX:#define _MIPS_SPFPSET 16
// MIPS32R6-MFPXX:#define __mips_fpr 0
// RUN: %clang_cc1 \
@@ -1716,30 +1737,35 @@
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32 %s
// MIPS32-MFP32:#define _MIPS_FPSET 16
+// MIPS32-MFP32:#define _MIPS_SPFPSET 32
// MIPS32-MFP32:#define __mips_fpr 32
// RUN: %clang_cc1 -target-feature +fp64 \
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP64 %s
// MIPS32-MFP64:#define _MIPS_FPSET 32
+// MIPS32-MFP64:#define _MIPS_SPFPSET 32
// MIPS32-MFP64:#define __mips_fpr 64
//
// RUN: %clang_cc1 -target-feature +single-float \
// RUN: -E -dM -triple=mips-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32SF %s
// MIPS32-MFP32SF:#define _MIPS_FPSET 32
+// MIPS32-MFP32SF:#define _MIPS_SPFPSET 16
// MIPS32-MFP32SF:#define __mips_fpr 0
// RUN: %clang_cc1 -target-feature +fp64 \
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-MFP64 %s
// MIPS64-MFP64:#define _MIPS_FPSET 32
+// MIPS64-MFP64:#define _MIPS_SPFPSET 32
// MIPS64-MFP64:#define __mips_fpr 64
// RUN: %clang_cc1 -target-feature -fp64 -target-feature +single-float \
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-NOMFP64 %s
// MIPS64-NOMFP64:#define _MIPS_FPSET 32
+// MIPS64-NOMFP64:#define _MIPS_SPFPSET 32
// MIPS64-NOMFP64:#define __mips_fpr 32
// RUN: %clang_cc1 -target-cpu mips32r6 \
@@ -1749,6 +1775,7 @@
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
// RUN: | FileCheck -match-full-lines -check-prefix MIPS-XXR6 %s
// MIPS-XXR6:#define _MIPS_FPSET 32
+// MIPS-XXR6:#define _MIPS_SPFPSET 32
// MIPS-XXR6:#define __mips_fpr 64
// MIPS-XXR6:#define __mips_nan2008 1
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