[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)

[Craig Topper via cfe-commits]

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@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
           CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
     return;
 
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
+  if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
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topperc wrote:

> Today, if you use software SCS on a platform without support they just fail, since the SCS won't be setup and gp(probably) points to invalid memory. Is it unreasonable to have it work the same in this case?

If the hardware shadow stack isn't set up, won't the instructions become silent NOPs rather than failing?

https://github.com/llvm/llvm-project/pull/68075