[clang] 81d8fa5 - [Clang][SVE2.1] Add svcntp prototype
Caroline Concatto via cfe-commits
cfe-commits at lists.llvm.org
Tue Oct 17 07:15:22 PDT 2023
Author: Caroline Concatto
Date: 2023-10-17T14:14:45Z
New Revision: 81d8fa5a1d01e1cd00865966957dba74b5e8613f
URL: https://github.com/llvm/llvm-project/commit/81d8fa5a1d01e1cd00865966957dba74b5e8613f
DIFF: https://github.com/llvm/llvm-project/commit/81d8fa5a1d01e1cd00865966957dba74b5e8613f.diff
LOG: [Clang][SVE2.1] Add svcntp prototype
As described in: https://github.com/ARM-software/acle/pull/257
Patch by : David Sherwood <david.sherwood at arm.com>
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D150961
Added:
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
Modified:
clang/include/clang/Basic/arm_sve.td
clang/include/clang/Basic/arm_sve_sme_incl.td
clang/lib/Sema/SemaChecking.cpp
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
index 894a0a1296b0473..07dc8cdece990be 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1867,4 +1867,6 @@ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, "aarch64_
let TargetGuard = "sve2p1" in {
def SVSCLAMP : SInst<"svclamp[_{d}]", "dddd", "csil", MergeNone, "aarch64_sve_sclamp", [], []>;
def SVUCLAMP : SInst<"svclamp[_{d}]", "dddd", "UcUsUiUl", MergeNone, "aarch64_sve_uclamp", [], []>;
+def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, "aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
+
}
diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td b/clang/include/clang/Basic/arm_sve_sme_incl.td
index 74c9b9266771b02..da15f1fb31847e6 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -246,6 +246,7 @@ def ImmCheck0_3 : ImmCheckType<15>; // 0..3
def ImmCheck0_0 : ImmCheckType<16>; // 0..0
def ImmCheck0_15 : ImmCheckType<17>; // 0..15
def ImmCheck0_255 : ImmCheckType<18>; // 0..255
+def ImmCheck2_4_Mul2 : ImmCheckType<19>; // 2, 4
class ImmCheck<int arg, ImmCheckType kind, int eltSizeArg = -1> {
int Arg = arg;
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index e121da8fac6d9b4..31b7e6cc8b8922a 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3120,6 +3120,11 @@ bool Sema::CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
HasError = true;
break;
+ case SVETypeFlags::ImmCheck2_4_Mul2:
+ if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 2, 4) ||
+ SemaBuiltinConstantArgMultiple(TheCall, ArgNum, 2))
+ HasError = true;
+ break;
}
}
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
new file mode 100644
index 000000000000000..18973a6467450a2
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
@@ -0,0 +1,119 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+#include <arm_sve.h>
+
+// CHECK-LABEL: @test_svcntp_c8_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c8_vlx2(svcount_t pnn) {
+ return svcntp_c8(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c8_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c8_vlx4(svcount_t pnn) {
+ return svcntp_c8(pnn, 4);
+}
+
+// CHECK-LABEL: @test_svcntp_c16_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c16_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c16_vlx2(svcount_t pnn) {
+ return svcntp_c16(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c16_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c16_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c16(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c16_vlx4(svcount_t pnn) {
+ return svcntp_c16(pnn, 4);
+}
+
+// CHECK-LABEL: @test_svcntp_c32_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c32_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c32_vlx2(svcount_t pnn) {
+ return svcntp_c32(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c32_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c32_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c32(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c32_vlx4(svcount_t pnn) {
+ return svcntp_c32(pnn, 4);
+}
+
+// CHECK-LABEL: @test_svcntp_c64_vlx2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c64_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c64_vlx2(svcount_t pnn) {
+ return svcntp_c64(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c64_vlx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svcntp_c64_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.c64(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c64_vlx4(svcount_t pnn) {
+ return svcntp_c64(pnn, 4);
+}
diff --git a/clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp b/clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
new file mode 100644
index 000000000000000..781757a2b9c23ec
--- /dev/null
+++ b/clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -triple aarch14-none-linux-gnu -target-feature +sve2p1 -fsyntax-only -verify %s
+
+// REQUIRES: aarch14-registered-target
+
+#include <arm_sve.h>
+
+void test_cntp(svcount_t c) {
+ svcntp_c8(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+ svcntp_c11(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+ svcntp_c32(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+ svcntp_c14(c, 1); // expected-error {{argument value 1 is outside the valid range [2, 4]}}
+
+ svcntp_c8(c, 3); // expected-error {{argument should be a multiple of 2}}
+ svcntp_c11(c, 3); // expected-error {{argument should be a multiple of 2}}
+ svcntp_c32(c, 3); // expected-error {{argument should be a multiple of 2}}
+ svcntp_c14(c, 3); // expected-error {{argument should be a multiple of 2}}
+}
+
More information about the cfe-commits
mailing list