[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)

[Yeting Kuo via cfe-commits]

================
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
           CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
     return;
 
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
+  if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
----------------
yetingk wrote:

> What if we're compiling for a platform that only uses the software shadow stack and does not support the hardware shadow stack even if the CPU supports it?

I think I should move the implement out of `emitSCSEpilogue`/`emitSCSPrologue` and enable hardware shadow stack by a new option, like `-riscv-hardware-shadow-stack`?

https://github.com/llvm/llvm-project/pull/68075