[clang] Remove experimental from Vector Crypto extensions (PR #69000)
Brandon Wu via cfe-commits
cfe-commits at lists.llvm.org
Fri Oct 13 08:23:51 PDT 2023
https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/69000
None
>From 521060552794304a5f6b31e38c25ab0a7a0353ff Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Fri, 13 Oct 2023 08:23:02 -0700
Subject: [PATCH] Remove experimental from Vector Crypto extensions
---
clang/lib/Sema/SemaChecking.cpp | 4 +-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 16 ++---
.../non-policy/non-overloaded/vaesdf.c | 14 ++--
.../non-policy/non-overloaded/vaesdm.c | 14 ++--
.../non-policy/non-overloaded/vaesef.c | 14 ++--
.../non-policy/non-overloaded/vaesem.c | 14 ++--
.../non-policy/non-overloaded/vaeskf1.c | 14 ++--
.../non-policy/non-overloaded/vaeskf2.c | 14 ++--
.../non-policy/non-overloaded/vaesz.c | 14 ++--
.../non-policy/non-overloaded/vandn.c | 16 ++---
.../non-policy/non-overloaded/vbrev.c | 14 ++--
.../non-policy/non-overloaded/vbrev8.c | 16 ++---
.../non-policy/non-overloaded/vclmul.c | 14 ++--
.../non-policy/non-overloaded/vclmulh.c | 14 ++--
.../non-policy/non-overloaded/vclz.c | 14 ++--
.../non-policy/non-overloaded/vcpopv.c | 2 +-
.../non-policy/non-overloaded/vctz.c | 14 ++--
.../non-policy/non-overloaded/vghsh.c | 14 ++--
.../non-policy/non-overloaded/vgmul.c | 14 ++--
.../non-policy/non-overloaded/vrev8.c | 16 ++---
.../non-policy/non-overloaded/vrol.c | 16 ++---
.../non-policy/non-overloaded/vror.c | 16 ++---
.../non-policy/non-overloaded/vsha2ch.c | 14 ++--
.../non-policy/non-overloaded/vsha2cl.c | 14 ++--
.../non-policy/non-overloaded/vsha2ms.c | 14 ++--
.../non-policy/non-overloaded/vsm3c.c | 14 ++--
.../non-policy/non-overloaded/vsm3me.c | 14 ++--
.../non-policy/non-overloaded/vsm4k.c | 14 ++--
.../non-policy/non-overloaded/vsm4r.c | 14 ++--
.../non-policy/non-overloaded/vwsll.c | 14 ++--
.../non-policy/overloaded/vaesdf.c | 14 ++--
.../non-policy/overloaded/vaesdm.c | 14 ++--
.../non-policy/overloaded/vaesef.c | 14 ++--
.../non-policy/overloaded/vaesem.c | 14 ++--
.../non-policy/overloaded/vaeskf1.c | 14 ++--
.../non-policy/overloaded/vaeskf2.c | 14 ++--
.../non-policy/overloaded/vaesz.c | 14 ++--
.../non-policy/overloaded/vandn.c | 16 ++---
.../non-policy/overloaded/vbrev.c | 14 ++--
.../non-policy/overloaded/vbrev8.c | 16 ++---
.../non-policy/overloaded/vclmul.c | 14 ++--
.../non-policy/overloaded/vclmulh.c | 14 ++--
.../non-policy/overloaded/vclz.c | 14 ++--
.../non-policy/overloaded/vcpopv.c | 2 +-
.../non-policy/overloaded/vctz.c | 14 ++--
.../non-policy/overloaded/vghsh.c | 14 ++--
.../non-policy/overloaded/vgmul.c | 14 ++--
.../non-policy/overloaded/vrev8.c | 16 ++---
.../non-policy/overloaded/vrol.c | 16 ++---
.../non-policy/overloaded/vror.c | 16 ++---
.../non-policy/overloaded/vsha2ch.c | 14 ++--
.../non-policy/overloaded/vsha2cl.c | 14 ++--
.../non-policy/overloaded/vsha2ms.c | 14 ++--
.../non-policy/overloaded/vsm3c.c | 14 ++--
.../non-policy/overloaded/vsm3me.c | 14 ++--
.../non-policy/overloaded/vsm4k.c | 14 ++--
.../non-policy/overloaded/vsm4r.c | 14 ++--
.../non-policy/overloaded/vwsll.c | 14 ++--
.../policy/non-overloaded/vaesdf.c | 14 ++--
.../policy/non-overloaded/vaesdm.c | 14 ++--
.../policy/non-overloaded/vaesef.c | 14 ++--
.../policy/non-overloaded/vaesem.c | 14 ++--
.../policy/non-overloaded/vaeskf1.c | 14 ++--
.../policy/non-overloaded/vaeskf2.c | 14 ++--
.../policy/non-overloaded/vaesz.c | 14 ++--
.../policy/non-overloaded/vandn.c | 16 ++---
.../policy/non-overloaded/vbrev.c | 14 ++--
.../policy/non-overloaded/vbrev8.c | 16 ++---
.../policy/non-overloaded/vclmul.c | 14 ++--
.../policy/non-overloaded/vclmulh.c | 14 ++--
.../policy/non-overloaded/vclz.c | 2 +-
.../policy/non-overloaded/vcpopv.c | 2 +-
.../policy/non-overloaded/vctz.c | 2 +-
.../policy/non-overloaded/vghsh.c | 14 ++--
.../policy/non-overloaded/vgmul.c | 14 ++--
.../policy/non-overloaded/vrev8.c | 16 ++---
.../policy/non-overloaded/vrol.c | 16 ++---
.../policy/non-overloaded/vror.c | 16 ++---
.../policy/non-overloaded/vsha2ch.c | 14 ++--
.../policy/non-overloaded/vsha2cl.c | 14 ++--
.../policy/non-overloaded/vsha2ms.c | 14 ++--
.../policy/non-overloaded/vsm3c.c | 14 ++--
.../policy/non-overloaded/vsm3me.c | 14 ++--
.../policy/non-overloaded/vsm4k.c | 14 ++--
.../policy/non-overloaded/vsm4r.c | 14 ++--
.../policy/non-overloaded/vwsll.c | 14 ++--
.../policy/overloaded/vaesdf.c | 14 ++--
.../policy/overloaded/vaesdm.c | 14 ++--
.../policy/overloaded/vaesef.c | 14 ++--
.../policy/overloaded/vaesem.c | 14 ++--
.../policy/overloaded/vaeskf1.c | 14 ++--
.../policy/overloaded/vaeskf2.c | 14 ++--
.../policy/overloaded/vaesz.c | 14 ++--
.../policy/overloaded/vandn.c | 16 ++---
.../policy/overloaded/vbrev.c | 14 ++--
.../policy/overloaded/vbrev8.c | 16 ++---
.../policy/overloaded/vclmul.c | 14 ++--
.../policy/overloaded/vclmulh.c | 14 ++--
.../policy/overloaded/vclz.c | 2 +-
.../policy/overloaded/vcpopv.c | 2 +-
.../policy/overloaded/vctz.c | 2 +-
.../policy/overloaded/vghsh.c | 14 ++--
.../policy/overloaded/vgmul.c | 14 ++--
.../policy/overloaded/vrev8.c | 16 ++---
.../policy/overloaded/vrol.c | 16 ++---
.../policy/overloaded/vror.c | 16 ++---
.../policy/overloaded/vsha2ch.c | 14 ++--
.../policy/overloaded/vsha2cl.c | 14 ++--
.../policy/overloaded/vsha2ms.c | 14 ++--
.../policy/overloaded/vsm3c.c | 14 ++--
.../policy/overloaded/vsm3me.c | 14 ++--
.../policy/overloaded/vsm4k.c | 14 ++--
.../policy/overloaded/vsm4r.c | 14 ++--
.../policy/overloaded/vwsll.c | 14 ++--
.../vaeskf1-out-of-range.c | 4 +-
.../vaeskf2-out-of-range.c | 4 +-
.../vsm3c-out-of-range.c | 4 +-
.../vsm4k-out-of-range.c | 4 +-
clang/test/Sema/zvk-invalid-vlen.c | 4 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++++------
llvm/lib/Target/RISCV/RISCVFeatures.td | 32 +++++-----
.../Analysis/CostModel/RISCV/int-bit-manip.ll | 2 +-
llvm/test/CodeGen/RISCV/attributes.ll | 64 +++++++++----------
.../CodeGen/RISCV/rvv/bitreverse-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-bitreverse.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 4 +-
.../rvv/fixed-vectors-shuffle-reverse.ll | 4 +-
.../RISCV/rvv/fixed-vectors-shuffle-rotate.ll | 8 +--
.../CodeGen/RISCV/rvv/fixed-vectors-vrol.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vror.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesdf.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesdm.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesef.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesem.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vaesz.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vandn.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vbrev.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vbrev8.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vclmul.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vclmulh.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vclz.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vcpopv.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vctz.ll | 4 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 4 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vghsh.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vgmul.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vrev8.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vrol.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vror.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsm3c.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsm3me.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsm4k.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsm4r.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vwsll.ll | 4 +-
llvm/test/MC/RISCV/rvv/zvbb-invalid.s | 2 +-
llvm/test/MC/RISCV/rvv/zvbb.s | 8 +--
llvm/test/MC/RISCV/rvv/zvbc.s | 8 +--
llvm/test/MC/RISCV/rvv/zvkb.s | 8 +--
llvm/test/MC/RISCV/rvv/zvkg.s | 8 +--
llvm/test/MC/RISCV/rvv/zvkned.s | 8 +--
llvm/test/MC/RISCV/rvv/zvknh.s | 16 ++---
llvm/test/MC/RISCV/rvv/zvksed.s | 8 +--
llvm/test/MC/RISCV/rvv/zvksh.s | 8 +--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 32 +++++-----
188 files changed, 1009 insertions(+), 1009 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 35b36db2049db09..504b5f5516c597c 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -4765,10 +4765,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
QualType Op2Type = TheCall->getArg(1)->getType();
QualType Op3Type = TheCall->getArg(2)->getType();
uint64_t ElemSize = Op1Type->isRVVType(32, false) ? 32 : 64;
- if (ElemSize == 64 && !TI.hasFeature("experimental-zvknhb"))
+ if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
return
Diag(TheCall->getBeginLoc(), diag::err_riscv_type_requires_extension)
- << Op1Type << "experimental-zvknhb";
+ << Op1Type << "zvknhb";
return CheckInvalidVLENandLMUL(TI, TheCall, *this, Op1Type, ElemSize << 2) ||
CheckInvalidVLENandLMUL(TI, TheCall, *this, Op2Type, ElemSize << 2) ||
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index ae584dc68719901..7bc080f05c32be8 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -205,14 +205,14 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
static const std::pair<const char *, RVVRequire> FeatureCheckList[] = {
{"64bit", RVV_REQ_RV64},
{"xsfvcp", RVV_REQ_Xsfvcp},
- {"experimental-zvbb", RVV_REQ_Zvbb},
- {"experimental-zvbc", RVV_REQ_Zvbc},
- {"experimental-zvkb", RVV_REQ_Zvkb},
- {"experimental-zvkg", RVV_REQ_Zvkg},
- {"experimental-zvkned", RVV_REQ_Zvkned},
- {"experimental-zvknha", RVV_REQ_Zvknha},
- {"experimental-zvksed", RVV_REQ_Zvksed},
- {"experimental-zvksh", RVV_REQ_Zvksh}};
+ {"zvbb", RVV_REQ_Zvbb},
+ {"zvbc", RVV_REQ_Zvbc},
+ {"zvkb", RVV_REQ_Zvkb},
+ {"zvkg", RVV_REQ_Zvkg},
+ {"zvkned", RVV_REQ_Zvkned},
+ {"zvknha", RVV_REQ_Zvknha},
+ {"zvksed", RVV_REQ_Zvksed},
+ {"zvksh", RVV_REQ_Zvksh}};
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
// in RISCVVEmitter.cpp.
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
index 7073c65233f65fc..5581903f7c99938 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
index 1b66240e9f2fcbc..7c17ee1209bf217 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
index c04092a5d9872a4..e9683b2d6e165d8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
index 88c33d87212fef1..d671877e2d035ae 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
index 3ef9aa473fcc2e0..b2d0e44baaf8617 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
index 94536358d51b067..5f74a026aa42a29 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
index bad34e2eb441404..950b5d8a5a14c1d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
index 4901b9bb4fdf640..696970bbc6c9fb6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
index 1e107dc37a27444..e5e01de0faa83e6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
index 471a0bb8a1df813..ebad4b2ed105e81 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
index 54c9aa71f846b2d..4388c6cd82c5067 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
index cf10d2566eb627f..e88b822792766b0 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
index 1f92b08e3f9598d..41539d4a3692f78 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
index 69eaed4d184e5b3..3b0399ba0b09412 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
index 26399c1ae7d4d27..05ee57d7f24faab 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
index b8fc94b251b9361..1c4f4c60a612e5b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
index f78ac856cb65ad7..bb09517aef987da 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
index b4187810de9f8f6..fe95c00ff72a9ee 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
index 4f64e5d6dc1fea7..056eaa04776b7e7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
index bf7a252950e1dcd..6ea9ef6741c64e7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
index 52002081ddf6f98..8b34dc3c19efb82 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
index e07a3375e0f9708..10cacf2abdaf26a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
index 0e3be9fdc436693..8389ebdc6b6dee0 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
index c6d1fe99d6015cc..abb2f181d86d3ef 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
index cf0fa32a5c35347..e73252783424e22 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
index 110dc4c3268ecd3..5ed418d6fc521a3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
index 1e8be7df16e8830..62a87e568c36a14 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
index a4c92e1ca05d958..2433ea25a1e7dd6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
index 59a01b3fc3ed0d2..c74c404673987ca 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
index ff6cf16b1143b53..0ee045d268e9a0b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
index 8c645d5bd1182d7..efabc470c1f965e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
index 72f2e963433a520..386a7b6f07de75a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
index cc68e5466809726..1f21d219bfd3dd6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
index 7c7b141728eb89e..0d854eb8271600c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
index 8e596fb1685e109..cfa0be575d87c44 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
index 0092b9d7980a6f9..d55ff590b4cf729 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
index 0bb47a67a4bb489..85ce64c07246995 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
index 637c7139ccac7c9..1a381e9527ef573 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
index 46ac3c8a7c0e587..c59bee48bdf66dd 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
index af323c79680d19a..326588ec0d6b976 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
index 9ea5ac50e3c2465..f6d3f71a530f946 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
index d73d656264405ef..901d4afb99568b3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
index 4b54f2e41eed124..1a005f0b8507e5b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
index c30dde2e0fbff94..0806bce202a3104 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
index 3a78395e15271b5..c18971a55fe6575 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
index c8b3ec5b445f5e9..77eadbfd409f166 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
index 672a35e972ddcb6..829fda0f7f524ee 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
index 6d992da031a05e3..5b53ffe400fb074 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
index e10541af38be6b8..498acb52430c158 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
index c95138b174992ea..1c8c1f467411fc1 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
index b616b49f663a495..d6d5703aca76144 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
index 3a3a8a62a11781d..7503caa7cfe5347 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
index 72837aeb5a66a06..bd175119a23464b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
index b25b2ade5806fe5..772f9750646b213 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
index 4eeecb894dda2bb..dcfa0d489616d54 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
index 6cfdbabb0951574..d539e84486284fd 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
index c75e3fa69453905..92ea64c35fd3fd4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
index b836ff37e58ab1d..a8ba9ebb012a03a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
index f5e47a9dee6d833..cca63f6c36e6f59 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
index 1f5281540d2d713..aa267e1e8f4474c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
index 1b94f3de632d025..62ad5d6cb5f6b50 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
index 1be7a48707c33ad..b5470b123ba876f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
index b4686e23c1a2798..9fba94e2da11c8d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
index 373e0b98fa326d5..bf6e47a63384c2c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
index 872d78295085fa5..d2d45d36d659d18 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
index 22c4afeea4fcc86..9e6cfab3bdca438 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
index 8c65318ccdaf38e..fa5b1ba151e794e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
index cdb4e942b85d254..e29e9d1783f3533 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
index 319dae3cfbffbf1..b859dddbc54a4c7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
index 61e74dc544ddf1f..58f8302963b78fd 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
index aac53850513d93d..cb08e2e8ea77ecf 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
index a8deabe51636ebf..0c5fec92313a080 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
index 6a145d47989471c..16df1f354c1f118 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
index 075f23d6e4eb704..7c1360a3cc7dae1 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
index d8777fc06762b07..f06ae391c13ab10 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
index 4a5d44b5becad2c..f7ca893d4f25271 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
index 2f6b10107b2d9c4..ed9f5798fecd768 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
index 3d7181bd08d101b..19a943d3e61f461 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
index f5477374d3a5b63..765a2c379577f02 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
index e85ea154d691188..b587814d818cb23 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
index fe3d94bc0fddc6d..0acda04fe8be52a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
index 2ee834858621b45..37029f054e70d48 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
index 4c8f35161a5d2a4..4602e3fe5dfe34c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
index 9a70fc032f8adeb..e68d71b029eb63a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
index c23649ce655479d..b7f7ae03db26e69 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
index f7d66d754fde40a..b70f6397253ffa4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
index cf3fab73f076ec4..035cfb37af2d82a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
index 8a93a7e5440a804..94dcab827679b76 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
index 8527cca1523187a..61bfa6d2e0e2305 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf1.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
index ec6bb1dd498a487..bfd0c8be7874fc1 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaeskf2.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
index de0ceaa06642122..0eea29555f384a8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
index 3f32c1c8e7423ea..ef441e7a68b1351 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
index b64e9660a971220..ec871463af7cffa 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
index f7064acc6af5f85..d661eaa74fb1e25 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
index 6aa9d6bf7f62fae..7f6c55b935ebf6d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
index 34ebdd2c44aa63c..2f1df38b8deb7f6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclmulh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
index ba7ad3a9f5ec544..583ccee98e5fa95 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
index 86b5915efd46a22..87905dfcedb989c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
index 5aed53bafb4d398..d714b90300c411e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
index 59c957debaa7f9e..ee5f6d7b4122ce3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vghsh.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
index eae136b614321ce..29355ce01cbd856 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vgmul.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
index 0f9fe962bab3977..bb036b1429f4d2b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
index d21e92248bd1049..ddcddd08f569320 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
index b166d1096a0dc3f..4142817ce5b9125 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
@@ -1,14 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkb \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkb \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
index baf99c80d3c85d7..3ab7cf12d13178c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ch.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
index 05a61a4149053a1..8b3952dfdc701e9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2cl.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
index b02aa384c850fbf..e9c7bbcf01cacc3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsha2ms.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
index e01fcd1c1bc0f1a..f6a100e21cb169f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3c.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
index 806d088faf109ce..9bdc66e60578492 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm3me.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
index cd10883d3c132d1..5c793379d390a98 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4k.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
index 06d173ff269c7ad..bd40da39f82e9c7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
index d6574c28dbef840..04f2e271f88bc14 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsll.c
@@ -1,13 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
-// RUN: -target-feature +experimental-zvbb \
-// RUN: -target-feature +experimental-zvbc \
-// RUN: -target-feature +experimental-zvkg \
-// RUN: -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvknhb \
-// RUN: -target-feature +experimental-zvksed \
-// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
+// RUN: -target-feature +zvbb \
+// RUN: -target-feature +zvbc \
+// RUN: -target-feature +zvkg \
+// RUN: -target-feature +zvkned \
+// RUN: -target-feature +zvknhb \
+// RUN: -target-feature +zvksed \
+// RUN: -target-feature +zvksh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
index 2062188634c4d64..5e71b719aed774a 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvkned -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvkned -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
index a0f8ad76c516af5..fb4fdd13f68cfaf 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvkned -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvkned -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
index a2238f01d230842..858df366b2cfdb1 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvksh -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvksh -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
index 56fa9ed53deb451..9e697acf4006263 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
@@ -1,7 +1,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN: -target-feature +experimental-zvksed -fsyntax-only -verify %s
+// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
+// RUN: -target-feature +zvksed -fsyntax-only -verify %s
#include <riscv_vector.h>
diff --git a/clang/test/Sema/zvk-invalid-vlen.c b/clang/test/Sema/zvk-invalid-vlen.c
index a737d620e7aa6ee..7eca3192ec14515 100644
--- a/clang/test/Sema/zvk-invalid-vlen.c
+++ b/clang/test/Sema/zvk-invalid-vlen.c
@@ -1,6 +1,6 @@
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvkned \
-// RUN: -target-feature +experimental-zvksh %s -fsyntax-only -verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvkned \
+// RUN: -target-feature +zvksh %s -fsyntax-only -verify
#include <riscv_vector.h>
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 72d33e1e65c8f58..864c764903b4cf8 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -137,6 +137,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zmmul", RISCVExtensionVersion{1, 0}},
+ {"zvbb", RISCVExtensionVersion{1, 0}},
+ {"zvbc", RISCVExtensionVersion{1, 0}},
+
{"zve32f", RISCVExtensionVersion{1, 0}},
{"zve32x", RISCVExtensionVersion{1, 0}},
{"zve64d", RISCVExtensionVersion{1, 0}},
@@ -146,6 +149,22 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zvfh", RISCVExtensionVersion{1, 0}},
{"zvfhmin", RISCVExtensionVersion{1, 0}},
+ // vector crypto
+ {"zvkb", RISCVExtensionVersion{1, 0}},
+ {"zvkg", RISCVExtensionVersion{1, 0}},
+ {"zvkn", RISCVExtensionVersion{1, 0}},
+ {"zvknc", RISCVExtensionVersion{1, 0}},
+ {"zvkned", RISCVExtensionVersion{1, 0}},
+ {"zvkng", RISCVExtensionVersion{1, 0}},
+ {"zvknha", RISCVExtensionVersion{1, 0}},
+ {"zvknhb", RISCVExtensionVersion{1, 0}},
+ {"zvks", RISCVExtensionVersion{1, 0}},
+ {"zvksc", RISCVExtensionVersion{1, 0}},
+ {"zvksed", RISCVExtensionVersion{1, 0}},
+ {"zvksg", RISCVExtensionVersion{1, 0}},
+ {"zvksh", RISCVExtensionVersion{1, 0}},
+ {"zvkt", RISCVExtensionVersion{1, 0}},
+
{"zvl1024b", RISCVExtensionVersion{1, 0}},
{"zvl128b", RISCVExtensionVersion{1, 0}},
{"zvl16384b", RISCVExtensionVersion{1, 0}},
@@ -174,27 +193,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"ztso", RISCVExtensionVersion{0, 1}},
- {"zvbb", RISCVExtensionVersion{1, 0}},
- {"zvbc", RISCVExtensionVersion{1, 0}},
-
{"zvfbfmin", RISCVExtensionVersion{0, 8}},
{"zvfbfwma", RISCVExtensionVersion{0, 8}},
-
- // vector crypto
- {"zvkb", RISCVExtensionVersion{1, 0}},
- {"zvkg", RISCVExtensionVersion{1, 0}},
- {"zvkn", RISCVExtensionVersion{1, 0}},
- {"zvknc", RISCVExtensionVersion{1, 0}},
- {"zvkned", RISCVExtensionVersion{1, 0}},
- {"zvkng", RISCVExtensionVersion{1, 0}},
- {"zvknha", RISCVExtensionVersion{1, 0}},
- {"zvknhb", RISCVExtensionVersion{1, 0}},
- {"zvks", RISCVExtensionVersion{1, 0}},
- {"zvksc", RISCVExtensionVersion{1, 0}},
- {"zvksed", RISCVExtensionVersion{1, 0}},
- {"zvksg", RISCVExtensionVersion{1, 0}},
- {"zvksh", RISCVExtensionVersion{1, 0}},
- {"zvkt", RISCVExtensionVersion{1, 0}},
};
static void verifyTables() {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 548579173f0ede4..417f17e42ad0bd1 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -561,14 +561,14 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
"'Zawrs' (Wait on Reservation Set)">;
def FeatureStdExtZvkb
- : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
+ : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true",
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def FeatureStdExtZvbb
- : SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
+ : SubtargetFeature<"zvbb", "HasStdExtZvbb", "true",
"'Zvbb' (Vector basic bit-manipulation instructions.)",
[FeatureStdExtZvkb]>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
@@ -576,32 +576,32 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
"'Zvbb' (Vector basic bit-manipulation instructions.)">;
def FeatureStdExtZvbc
- : SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
+ : SubtargetFeature<"zvbc", "HasStdExtZvbc", "true",
"'Zvbc' (Vector Carryless Multiplication)">;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
- : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
+ : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true",
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def FeatureStdExtZvkned
- : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
+ : SubtargetFeature<"zvkned", "HasStdExtZvkned", "true",
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def FeatureStdExtZvknha
- : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
+ : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true",
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def FeatureStdExtZvknhb
- : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
+ : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true",
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
[FeatureStdExtZvknha]>;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
@@ -609,59 +609,59 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def FeatureStdExtZvksed
- : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
+ : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true",
"'Zvksed' (SM4 Block Cipher Instructions)">;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
def FeatureStdExtZvksh
- : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
+ : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true",
"'Zvksh' (SM3 Hash Function Instructions)">;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
def FeatureStdExtZvkt
- : SubtargetFeature<"experimental-zvkt", "HasStdExtZvkt", "true",
+ : SubtargetFeature<"zvkt", "HasStdExtZvkt", "true",
"'Zvkt' (Vector Data-Independent Execution Latency)">;
// Zvk short-hand extensions
def FeatureStdExtZvkn
- : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
+ : SubtargetFeature<"zvkn", "HasStdExtZvkn", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvknc
- : SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
+ : SubtargetFeature<"zvknc", "HasStdExtZvknc", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvkn and Zvbc.",
[FeatureStdExtZvkn, FeatureStdExtZvbc]>;
def FeatureStdExtZvkng
- : SubtargetFeature<"experimental-zvkng", "HasStdExtZvkng", "true",
+ : SubtargetFeature<"zvkng", "HasStdExtZvkng", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvkn and Zvkg.",
[FeatureStdExtZvkn, FeatureStdExtZvkg]>;
def FeatureStdExtZvks
- : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
+ : SubtargetFeature<"zvks", "HasStdExtZvks", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvksc
- : SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",
+ : SubtargetFeature<"zvksc", "HasStdExtZvksc", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvks and Zvbc.",
[FeatureStdExtZvks, FeatureStdExtZvbc]>;
def FeatureStdExtZvksg
- : SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true",
+ : SubtargetFeature<"zvksg", "HasStdExtZvksg", "true",
"This extension is shorthand for the following set of "
"other extensions: Zvks and Zvkg.",
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
diff --git a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
index 7798352e6bda77d..380f65b19b8fa16 100644
--- a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,NOZVBB
; Vector ctpop exists only under ZVBB
-; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d,+experimental-zvbb -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,ZVBB
+; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d,+zvbb -riscv-v-vector-bits-min=-1 | FileCheck %s --check-prefixes=CHECK,ZVBB
define void @bswap() {
; CHECK-LABEL: 'bswap'
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index c28594088dac5cd..f40f6b0b9e1c1aa 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -64,22 +64,22 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s
; RUN: llc -mtriple=riscv32 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHPM %s
; RUN: llc -mtriple=riscv32 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV32ZVKNC %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV32ZVKNG %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvksc %s -o - | FileCheck --check-prefix=RV32ZVKSC %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvknc %s -o - | FileCheck --check-prefix=RV32ZVKNC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvkng %s -o - | FileCheck --check-prefix=RV32ZVKNG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvksc %s -o - | FileCheck --check-prefix=RV32ZVKSC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
@@ -154,22 +154,22 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
; RUN: llc -mtriple=riscv64 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHPM %s
; RUN: llc -mtriple=riscv64 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV64ZVKNC %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV64ZVKNG %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvksc %s -o - | FileCheck --check-prefix=RV64ZVKSC %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvknc %s -o - | FileCheck --check-prefix=RV64ZVKNC %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvkng %s -o - | FileCheck --check-prefix=RV64ZVKNG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+zvksc %s -o - | FileCheck --check-prefix=RV64ZVKSC %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
index 3514fa66f5886d3..19ae26d24242605 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @bitreverse_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-LABEL: bitreverse_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
index 7698f860589aaf1..486c00ee2d936e8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.bitreverse.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
index c55399b502471a3..d3fce3caf8aef95 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
define <vscale x 1 x i16> @bswap_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-LABEL: bswap_nxv1i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index 6aac13a0bcbb873..4e160707163aee0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
declare <vscale x 1 x i16> @llvm.vp.bswap.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
index d78d67d5e359871..9684eef1ee2837f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
@@ -5,8 +5,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @ctlz_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-ZVE64X-LABEL: ctlz_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index f479937ba2fc727..a96b671f86242cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
index 1a2b2640ca4fe4c..8952ab433148589 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @ctpop_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-LABEL: ctpop_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
index 9767ba4bbc3b7a6..f862c79d05c7dba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.ctpop.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index fb4735240904682..40a25d575bd9dcf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -5,8 +5,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64,RV64F
; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32,RV32D
; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64,RV64D
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-ZVE64X-LABEL: cttz_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index 1dda8aa458d9069..596e32de6834bf4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -3,9 +3,9 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
declare <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
index 74a3153b5839dc6..1957829b1288ab9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
@@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,LMULMAX2-RV64
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,LMULMAX1-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @bitreverse_v8i16(ptr %x, ptr %y) {
; RV32-LABEL: bitreverse_v8i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
index 628a3e072abcd01..41f74255c31b06e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
@@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2-RV64
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
define void @bswap_v8i16(ptr %x, ptr %y) {
; CHECK-LABEL: bswap_v8i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index 9c30d3ac71679ba..878ffd3ae5c20f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -11,8 +11,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @ctlz_v16i8(ptr %x, ptr %y) nounwind {
; CHECK-LABEL: ctlz_v16i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
index 0b2a44fa14526be..82580de924381e9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
@@ -3,8 +3,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2,LMULMAX2-RV64
; RUN: llc -mtriple=riscv32 -mattr=+m,+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @ctpop_v16i8(ptr %x, ptr %y) {
; CHECK-LABEL: ctpop_v16i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index 1b422730f2ac7b1..2adc6a935689083 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -11,8 +11,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1-RV64
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+d -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=LMULMAX8
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB
define void @cttz_v16i8(ptr %x, ptr %y) nounwind {
; CHECK-LABEL: cttz_v16i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
index 70b19856fc536c5..8f9f1c2729fc711 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
@@ -5,8 +5,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-UNKNOWN
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-256
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-512
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB
;
; VECTOR_REVERSE - masks
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
index 49cd4b85693b60d..f67b8ac325c6bf2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvfh,+zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X
define <8 x i1> @shuffle_v8i1_as_i8_1(<8 x i1> %v) {
; CHECK-LABEL: shuffle_v8i1_as_i8_1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
index 99a933985a351d2..e719c6f374973a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
index aa63013eec12024..c7c757efc1badc7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
declare <1 x i8> @llvm.fshr.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll b/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
index b02c63b29cb8bc0..1ad30fa264e0c5f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll b/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
index bc1a7c22f373cbb..b7a4a11663310a0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesef.ll b/llvm/test/CodeGen/RISCV/rvv/vaesef.ll
index 44ab69f0a9a838e..bd8a7cb94ab0fb5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesef.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesef.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesef.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesem.ll b/llvm/test/CodeGen/RISCV/rvv/vaesem.ll
index 0f35ce017c28c97..21b5e5942e319b7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesem.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesem.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesem.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll b/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
index 681ff0d3bf6be3e..7988a9f99c85eb1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll b/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
index ba37f69c380cb9e..5abe0821d22996d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaeskf2.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaesz.ll b/llvm/test/CodeGen/RISCV/rvv/vaesz.ll
index 5c08cf3013365ab..ee089f1e77cc357 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaesz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaesz.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkned \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
index f716984599e3f29..a1b1c015369c8ca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
define <vscale x 1 x i8> @vandn_vv_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {
; CHECK-LABEL: vandn_vv_nxv1i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
index c1e85802d3732df..4ff6e5660b25d96 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64
declare <vscale x 1 x i8> @llvm.vp.and.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
declare <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn.ll b/llvm/test/CodeGen/RISCV/rvv/vandn.ll
index 044b0467d6d20f7..a5e29d488da522a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vbrev.ll b/llvm/test/CodeGen/RISCV/rvv/vbrev.ll
index f95e43fb5fcb8c6..7e86414990b9b68 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vbrev.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vbrev.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll b/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
index 64ca9aff6af3631..91a65a1b3b17564 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vclmul.ll b/llvm/test/CodeGen/RISCV/rvv/vclmul.ll
index 44aae02cee6f5ec..1184d4b96cc5e33 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vclmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vclmul.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll b/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
index 673c63837c77583..98befd81ace0c68 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbc \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbc \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vclz.ll b/llvm/test/CodeGen/RISCV/rvv/vclz.ll
index aaa760106e91c58..6a9b84c1f43f4f4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vclz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vclz.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll b/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
index 99dfc3be9a00c05..523a2a3ec775082 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcpopv.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vctz.ll b/llvm/test/CodeGen/RISCV/rvv/vctz.ll
index 763fac014811729..5089010e2663a24 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vctz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vctz.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index b8f2afd194e46d6..6ebe8e0954698a9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV64 %s
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
; Integers
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 4b5edaa1cd3f7d8..5cdbac5ac83d2bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB
; Integers
diff --git a/llvm/test/CodeGen/RISCV/rvv/vghsh.ll b/llvm/test/CodeGen/RISCV/rvv/vghsh.ll
index 977386dee8f524a..291d505d8faaf71 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vghsh.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vghsh.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vgmul.ll b/llvm/test/CodeGen/RISCV/rvv/vgmul.ll
index d4ce44d9eec2be0..4498f71008704f7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vgmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vgmul.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkg \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkg \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrev8.ll b/llvm/test/CodeGen/RISCV/rvv/vrev8.ll
index 3a09c971372681e..ef58b755ba4cdf9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrev8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrev8.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
index 2d8b3647163ea0d..fc6af87e473ef33 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrol.ll b/llvm/test/CodeGen/RISCV/rvv/vrol.ll
index 05277d1bd718fab..c47afed6f7756ac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrol.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
index f8c1bb5194f11bb..13a584a67328701 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
declare <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vror.ll b/llvm/test/CodeGen/RISCV/rvv/vror.ll
index 818bb069e798d7a..1e8fa86119b6b31 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vror.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
index 52c43f9713a6080..f3a177299ed9e6e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
index 49ae2858e1461ba..be1da902cbe39fd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
index d26c9f5a373862f..53fd59cb8990d77 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvknha,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknha,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvknha,+experimental-zvknhb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknha,+zvknhb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll b/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
index 16d29028c1e30f1..17d59682c104fa0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm3c.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll b/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
index ed7f21312c5e22a..8d7c2e5975df1bf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm3me.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksh \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksh \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll b/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
index fe2bb9a77bcc4aa..91095da81eeb4e0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm4k.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll b/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
index f9da81eb9575a12..cb836596fdfd1d6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvksed \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vv.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
index f45a281c2e00c83..8a0af38f724c4cb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
; ==============================================================================
; i32 -> i64
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
index 995adaf6e185ab7..e7ac8ee1756415d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64
; ==============================================================================
; i32 -> i64
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll.ll
index 9909fc62d0c80cd..9711afb2aafbf05 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb \
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8(
diff --git a/llvm/test/MC/RISCV/rvv/zvbb-invalid.s b/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
index 46bde3a8ce7029e..ca581de02fd603f 100644
--- a/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvbb-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+experimental-zvbb %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+zvbb %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
vwsll.vv v2, v2, v4
diff --git a/llvm/test/MC/RISCV/rvv/zvbb.s b/llvm/test/MC/RISCV/rvv/zvbb.s
index 58b28f88868a379..7fd22b8c40cbb5d 100644
--- a/llvm/test/MC/RISCV/rvv/zvbb.s
+++ b/llvm/test/MC/RISCV/rvv/zvbb.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvbb %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvbb %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvbb - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvbb %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvbb - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvbb %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vbrev.v v10, v9, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvbc.s b/llvm/test/MC/RISCV/rvv/zvbc.s
index 9c1f7873248d903..b32349a2db1335d 100644
--- a/llvm/test/MC/RISCV/rvv/zvbc.s
+++ b/llvm/test/MC/RISCV/rvv/zvbc.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve64x --mattr=+experimental-zvbc %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve64x --mattr=+zvbc %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \
-# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvbc - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+zvbc %s \
+# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+zvbc - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+zvbc %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vclmul.vv v10, v9, v8
diff --git a/llvm/test/MC/RISCV/rvv/zvkb.s b/llvm/test/MC/RISCV/rvv/zvkb.s
index ca4ef960170f7d6..7722e4b3e6a3bc7 100644
--- a/llvm/test/MC/RISCV/rvv/zvkb.s
+++ b/llvm/test/MC/RISCV/rvv/zvkb.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvkb %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkb %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvkb - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkb %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vandn.vv v10, v9, v8, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvkg.s b/llvm/test/MC/RISCV/rvv/zvkg.s
index 35b94e96fee549d..f2016bc116b656b 100644
--- a/llvm/test/MC/RISCV/rvv/zvkg.s
+++ b/llvm/test/MC/RISCV/rvv/zvkg.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvkg %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkg - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkg %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvkg - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkg %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vghsh.vv v10, v9, v8
diff --git a/llvm/test/MC/RISCV/rvv/zvkned.s b/llvm/test/MC/RISCV/rvv/zvkned.s
index aa78ce7f858f98c..6ab9c918f354139 100644
--- a/llvm/test/MC/RISCV/rvv/zvkned.s
+++ b/llvm/test/MC/RISCV/rvv/zvkned.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkned %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvkned %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkned - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkned %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvkned - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvkned %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vaesdf.vv v10, v9
diff --git a/llvm/test/MC/RISCV/rvv/zvknh.s b/llvm/test/MC/RISCV/rvv/zvknh.s
index a00fdcc50ea74e4..cafe9a80954d8eb 100644
--- a/llvm/test/MC/RISCV/rvv/zvknh.s
+++ b/llvm/test/MC/RISCV/rvv/zvknh.s
@@ -1,16 +1,16 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvknha %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+zvknhb %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvknha - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvknha %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvknha - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
-# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvknhb - \
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+zvknhb %s \
+# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+zvknhb - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvknha %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+zvknhb %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
diff --git a/llvm/test/MC/RISCV/rvv/zvksed.s b/llvm/test/MC/RISCV/rvv/zvksed.s
index a8e298c8de3ec6c..757358d460cddc7 100644
--- a/llvm/test/MC/RISCV/rvv/zvksed.s
+++ b/llvm/test/MC/RISCV/rvv/zvksed.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvksed %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksed %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvksed - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksed %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vsm4k.vi v10, v9, 7
diff --git a/llvm/test/MC/RISCV/rvv/zvksh.s b/llvm/test/MC/RISCV/rvv/zvksh.s
index 9affe060caa3ee0..d78d08d3c9a0bc2 100644
--- a/llvm/test/MC/RISCV/rvv/zvksh.s
+++ b/llvm/test/MC/RISCV/rvv/zvksh.s
@@ -1,11 +1,11 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+zvksh %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh - \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksh %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+zvksh - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+zvksh %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vsm3c.vi v10, v9, 7
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 90e26a23e87c205..94a3808bccffc54 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -682,6 +682,8 @@ R"(All available -march extensions for RISC-V
zksed 1.0
zksh 1.0
zkt 1.0
+ zvbb 1.0
+ zvbc 1.0
zve32f 1.0
zve32x 1.0
zve64d 1.0
@@ -689,6 +691,20 @@ R"(All available -march extensions for RISC-V
zve64x 1.0
zvfh 1.0
zvfhmin 1.0
+ zvkb 1.0
+ zvkg 1.0
+ zvkn 1.0
+ zvknc 1.0
+ zvkned 1.0
+ zvkng 1.0
+ zvknha 1.0
+ zvknhb 1.0
+ zvks 1.0
+ zvksc 1.0
+ zvksed 1.0
+ zvksg 1.0
+ zvksh 1.0
+ zvkt 1.0
zvl1024b 1.0
zvl128b 1.0
zvl16384b 1.0
@@ -732,24 +748,8 @@ Experimental extensions
zacas 1.0
zfbfmin 0.8
ztso 0.1
- zvbb 1.0
- zvbc 1.0
zvfbfmin 0.8
zvfbfwma 0.8
- zvkb 1.0
- zvkg 1.0
- zvkn 1.0
- zvknc 1.0
- zvkned 1.0
- zvkng 1.0
- zvknha 1.0
- zvknhb 1.0
- zvks 1.0
- zvksc 1.0
- zvksed 1.0
- zvksg 1.0
- zvksh 1.0
- zvkt 1.0
smaia 1.0
ssaia 1.0
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