[clang] c661c4f - [AIX] recognize vsr in inline asm for AIX (#68476)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Oct 11 17:54:50 PDT 2023
Author: Chen Zheng
Date: 2023-10-12T08:54:45+08:00
New Revision: c661c4f57613b5f85af94ee4e905708e0ba820f8
URL: https://github.com/llvm/llvm-project/commit/c661c4f57613b5f85af94ee4e905708e0ba820f8
DIFF: https://github.com/llvm/llvm-project/commit/c661c4f57613b5f85af94ee4e905708e0ba820f8.diff
LOG: [AIX] recognize vsr in inline asm for AIX (#68476)
Extend `PPCTargetInfo::getGCCAddlRegNames()` to aix as well. The
definition should be common between Linux PPC and AIX PPC.
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
Removed:
################################################################################
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 4e895cc7310c00e..0d87a3a4e8c20f3 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -753,6 +753,8 @@ void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
}
}
+// Make sure that registers are added in the correct array index which should be
+// the DWARF number for PPC registers.
const char *const PPCTargetInfo::GCCRegNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
"r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
@@ -807,6 +809,7 @@ ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definition "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which run on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
@@ -828,10 +831,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
- return llvm::ArrayRef(GCCAddlRegNames);
- else
- return TargetInfo::getGCCAddlRegNames();
+ return llvm::ArrayRef(GCCAddlRegNames);
}
static constexpr llvm::StringLiteral ValidCPUNames[] = {
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..842e9b533a97454 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,12 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// This case is to test VSX register support in the clobbers list for inline asm.
void testVSX (void) {
@@ -9,12 +15,12 @@ void testVSX (void) {
unsigned int *dbell=&a;
int d;
__asm__ __volatile__ (
- "lxvw4x %%vs32, 0, %2\n\t"
- "stxvw4x %%vs32, 0, %1"
+ "lxvw4x 32, 0, %2\n\t"
+ "stxvw4x 32, 0, %1"
: "=m"(*(volatile unsigned int*)(dbell))
: "r" (dbell), "r" (&d)
: "vs32"
);
}
-// CHECK: call void asm sideeffect "lxvw4x %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{vs32}"
+// CHECK: call void asm sideeffect "lxvw4x 32, 0, $2\0A\09stxvw4x 32, 0, $1", "=*m,r,r,~{vs32}"
More information about the cfe-commits
mailing list